UPD78F0533AGB-GAH-AX Renesas Electronics America, UPD78F0533AGB-GAH-AX Datasheet - Page 294
UPD78F0533AGB-GAH-AX
Manufacturer Part Number
UPD78F0533AGB-GAH-AX
Description
MCU 8BIT 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet
1.UPD78F0500MC-5A4-A.pdf
(982 pages)
Specifications of UPD78F0533AGB-GAH-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
55
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0533AGB-GAH-AX
Manufacturer:
RENESAS
Quantity:
460
Company:
Part Number:
UPD78F0533AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Note Care must be exercised when setting TOC0n. For details, see 7.3 (3) 16-bit timer output control register
Remark n = 0:
0n (TOC0n).
<1> Count operation start flow
<2> Count operation stop flow
TO0n output control bit
n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products
(TMC0n3, TMC0n2)
Figure 7-23. Example of Software Processing for Square-Wave Output Function
(TOC0n1, TOE0n)
INTTM00n signal
CR00n register
TM0n register
TMC0n3, TMC0n2 bits = 11
TMC0n3, TMC0n2 bits = 00
Operable bits
TO0n output
78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2,
78K0/KD2 products
Register initial setting
TOC0n register
PRM0n register,
CRC0n register,
CR00n register,
0000H
port setting
START
STOP
00
Note
<1>
,
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
N
Initial setting of these registers is performed before
setting the TMC0n3 and TMC0n2 bits to 11.
Starts count operation
The counter is initialized and counting is stopped
by clearing the TMC0n3 and TMC0n2 bits to 00.
N
11
N
N
<2>
00
294
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