UPD78F0533AGB-GAH-AX Renesas Electronics America, UPD78F0533AGB-GAH-AX Datasheet - Page 574

• Manufacturer Part Number: UPD78F0533AGB-GAH-AX
• Description: MCU 8BIT 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0533AGB-GAH-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 55
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
18.5.6 Wait
data (i.e., is in a wait state).
canceled for both the master and slave devices, the next data transfer can begin.
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
The wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive
Setting the SCL0 pin to low level notifies the communication partner of the wait state. When wait state has been
(1) When master device has a nine-clock wait and slave device has an eight-clock wait
(master transmits, slave receives, and ACKE0 = 1)
Transfer lines
Master
Slave
ACKE0
SDA0
SCL0
SCL0
SCL0
IIC0
IIC0
H
D2
6
6
Master returns to high
impedance but slave
is in wait state (low level).
Wait after output
of eighth clock
D1
7
7
Figure 18-18. Wait (1/2)
D0
8
8
Wait from slave
9
ACK
Wait after output
of ninth clock
9
FFH is written to IIC0 or WREL0 is set to 1
CHAPTER 18 SERIAL INTERFACE IIC0
Wait from master
IIC0 data write (cancel wait)
D7
1
1
D6
2
2
D5
3
3
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