UPD78F0533AGB-GAH-AX Renesas Electronics America, UPD78F0533AGB-GAH-AX Datasheet - Page 948
UPD78F0533AGB-GAH-AX
Manufacturer Part Number
UPD78F0533AGB-GAH-AX
Description
MCU 8BIT 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet
1.UPD78F0500MC-5A4-A.pdf
(982 pages)
Specifications of UPD78F0533AGB-GAH-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
55
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Company:
Part Number:
UPD78F0533AGB-GAH-AX
Manufacturer:
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Quantity:
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Part Number:
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78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Clock
generator
X1/XT1
oscillator
Function Details of Function
MCM: Main clock
mode register
OSTC: Oscillation
stabilization time
counter status
register
OSTS: Oscillation
stabilization time
select register
−
XSEL can be changed only once after a reset release.
Do not rewrite MCM0 when the CPU clock operates with the subsystem clock.
A clock other than f
the setting of XSEL and MCM0.
• Watchdog timer (operates with internal low-speed oscillation clock)
• When “f
• Peripheral hardware selects the external clock as the clock source
After the above time has elapsed, the bits are set to 1 in order from MOST11 and
remain 1.
The oscillation stabilization time counter counts up to the oscillation stabilization time
set by OSTS. If the STOP mode is entered and then released while the internal
high-speed oscillation clock is being used as the CPU clock, set the oscillation
stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS
before executing the STOP instruction.
Do not change the value of the OSTS register during the X1 clock oscillation
stabilization time.
The oscillation stabilization time counter counts up to the oscillation stabilization time
set by OSTS. If the STOP mode is entered and then released while the internal
high-speed oscillation clock is being used as the CPU clock, set the oscillation
stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed
by the broken lines in the Figures 6-12 and 6-13 to avoid an adverse effect from
wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a
• Always make the ground point of the oscillator capacitor the same potential as V
• Do not fetch signals from the oscillator.
Note that the XT1 oscillator is designed as a low-amplitude circuit for reducing power
consumption.
When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with
XT1, resulting in malfunctioning.
(operates with internal low-speed oscillation clock)
(Except when the external count clock of TM0n (n = 0, 1) is selected (TI00n pin
valid edge))
OSTS
OSTS
signal line through which a high fluctuating current flows.
Do not ground the capacitor to a ground pattern through which a high current
flows.
RL
”, “f
RL
/2
PRS
7
”, or “f
is supplied to the following peripheral functions regardless of
RL
/2
9
” is selected as the count clock for 8-bit timer H1
Cautions
APPENDIX D LIST OF CAUTIONS
SS
.
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