UPD78F0533AGB-GAH-AX Renesas Electronics America, UPD78F0533AGB-GAH-AX Datasheet - Page 582
UPD78F0533AGB-GAH-AX
Manufacturer Part Number
UPD78F0533AGB-GAH-AX
Description
MCU 8BIT 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet
1.UPD78F0500MC-5A4-A.pdf
(982 pages)
Specifications of UPD78F0533AGB-GAH-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
55
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0533AGB-GAH-AX
Manufacturer:
RENESAS
Quantity:
460
Company:
Part Number:
UPD78F0533AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
SDA0
SCL0
Remark
Communication reservations are accepted via the following timing. After bit 1 (STD0) of IIC status register 0
(IICS0) is set to 1, a communication reservation can be made by setting bit 1 (STT0) of IIC control register 0
(IICC0) to 1 before a stop condition is detected.
Figure 18-22 shows the communication reservation protocol.
SDA0
SPD0
STD0
SCL0
Hardware processing
Program processing
1
IIC0:
STT0:
STD0: Bit 1 of IIC status register 0 (IICS0)
SPD0: Bit 0 of IIC status register 0 (IICS0)
2
3
Figure 18-21. Timing for Accepting Communication Reservations
IIC shift register 0
Bit 1 of IIC control register 0 (IICC0)
STT0 = 1
Communi-
cation
reservation
4
Figure 18-20. Communication Reservation Timing
5
6
7
Standby mode
Generate by master device with bus mastership
8
9
Set SPD0
and
INTIIC0
CHAPTER 18 SERIAL INTERFACE IIC0
Write to
IIC0
Set
STD0
1
2
3
4
5
6
582
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