UPD78F1142AGB-GAH-AX Renesas Electronics America, UPD78F1142AGB-GAH-AX Datasheet - Page 172
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UPD78F1142AGB-GAH-AX
Manufacturer Part Number
UPD78F1142AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1142AGB-GAH-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Company:
Part Number:
UPD78F1142AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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170
(2) Example of setting procedure when using the subsystem clock as the CPU clock
(3) Example of setting procedure when stopping the subsystem clock
<1> Setting subsystem clock oscillation
<2> Setting the subsystem clock as the source clock of the CPU clock (CKC register)
Caution When the subsystem clock is used as the CPU clock, the subsystem clock is also supplied to
<1> Confirming the CPU clock status (CKC register)
<2> Stopping the subsystem clock (CSC register)
Cautions 1. Be sure to confirm that CLS = 0 when setting XTSTOP to 1.
(See 5.6.3 (1) Example of setting procedure when oscillating the subsystem clock.)
Note The setting of <1> is not necessary when while the subsystem clock is operating.
When CLS = 1, the subsystem clock is supplied to the CPU, so change the CPU clock to the internal
high-speed oscillation clock or high-speed system clock.
Transition Diagram or Table 5-5 Changing CPU Clock for the conditions to change the subsystem
clock to another clock.)
When XTSTOP is set to 1, subsystem clock is stopped.
Confirm with CLS and MCS that the CPU is operating on a clock other than the subsystem clock.
CSS
CLS
the peripheral hardware (except the real-time counter, clock output/buzzer output, and
watchdog timer).
guaranteed.
chapters describing the various peripheral hardware as well as CHAPTER 27 ELECTRICAL
SPECIFICATIONS
SPECIFICATIONS ((A) GRADE PRODUCTS).
0
0
1
1
2. The subsystem clock oscillation cannot be stopped using the STOP instruction.
peripheral hardware if it is operating on the subsystem clock.
f
SUB
MCS
/2
0
1
×
For the operating characteristics of the peripheral hardware, refer to the
Internal high-speed oscillation clock
High-speed system clock
Subsystem clock
At this time, the operations of the A/D converter and IIC0 are not
(STANDARD
CHAPTER 5 CLOCK GENERATOR
Selection of CPU/Peripheral Hardware Clock (f
User’s Manual U17854EJ9V0UD
Note
PRODUCTS)
CPU Clock Status
and
(See Figure 5-15 CPU Clock Status
CHAPTER
CLK
)
28
In addition, stop the
ELECTRICAL
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