UPD78F1142AGB-GAH-AX Renesas Electronics America, UPD78F1142AGB-GAH-AX Datasheet - Page 453
UPD78F1142AGB-GAH-AX
Manufacturer Part Number
UPD78F1142AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1142AGB-GAH-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1142AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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<R>
11.7.1 Address field transmission
for transfer (slave). After a start condition is generated, an address (7 bits) and a transfer direction (1 bit) are
transmitted in one frame.
Note To perform communication via simplified I
Target channel
Pins used
Interrupt
Error detection flag
Transfer data length
Transfer rate
Data level
Parity bit
Stop bit
Data direction
Address field transmission is a transmission operation that first executes in I
Simplified I
for the port output mode registers (POM0) (see 4.3 Registers Controlling Port Function for details). When
communicating with an external device with a different potential, set the N-ch open-drain output (V
mode (POM04 = 1) also for the clock input/output pins (SCL10) (see 4.4.4 Connecting to external device
with different potential (2.5 V, 3 V) for details).
2
C
Channel 2 of SAU0
SCL10, SDA10
INTIIC10
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Parity error detection flag (PEF02)
8 bits (transmitted with specifying the higher 7 bits as address and the least significant bit as R/W
control)
Max. f
However, the following condition must be satisfied in each mode of I
• Max. 400 kHz (first mode)
• Max. 100 kHz (standard mode)
Forward output (default: high level)
No parity bit
Appending 1 bit (for ACK reception timing)
MSB first
MCK
/4 [Hz] (SDR02[15:9] = 1 or more)
Note
CHAPTER 11 SERIAL ARRAY UNIT
User’s Manual U17854EJ9V0UD
2
C, set the N-ch open-drain output (V
f
IIC10
MCK
: Operation clock (MCK) frequency of target channel
2
C communication to identify the target
2
C.
DD
tolerance) mode (POM03 = 1)
DD
tolerance)
451
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