UPD78F1142AGB-GAH-AX Renesas Electronics America, UPD78F1142AGB-GAH-AX Datasheet - Page 482
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UPD78F1142AGB-GAH-AX
Manufacturer Part Number
UPD78F1142AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1142AGB-GAH-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1142AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Symbol
IICC0
Notes 1. The IICS0 register, the STCF and IICBSY bits of the IICF0 register, and the CLD0 and DAD0
Caution The start condition is detected immediately after I
WREL0
Be sure to set this bit (1) while the SCL0 and SDA0 lines are at high level.
Condition for clearing (IICE0 = 0)
• Cleared by instruction
• Reset
The standby mode following exit from communications remains in effect until the following communications entry
conditions are met.
• After a stop condition is detected, restart is in master mode.
• An address match or extension code reception occurs after the start condition.
Condition for clearing (LREL0 = 0)
• Automatically cleared after execution
• Reset
When WREL0 is set (wait canceled) during the wait period at the ninth clock pulse in the transmission status (TRC0 =
1), the SDA0 line goes into the high impedance state (TRC0 = 0).
Condition for clearing (WREL0 = 0)
• Automatically cleared after execution
• Reset
LREL0
IICE0
IICE0
<7>
0
1
0
1
0
1
Note 2
Note 2
2. The signal of this bit is invalid while IICE0 is 0.
After reset: 00H
while the SCL0 line is at high level and the SDA0 line is at low level. Immediately after
enabling I
instruction.
bits of the IICCL0 register are reset.
Stop operation. Reset IIC status register 0 (IICS0)
Enable operation.
Normal operation
This exits from the current communications and sets standby mode. This setting is automatically cleared
to 0 after being executed.
Its uses include cases in which a locally irrelevant extension code has been received.
The SCL0 and SDA0 lines are set to high impedance.
The following flags of IIC control register 0 (IICC0) and IIC status register 0 (IICS0) are cleared to 0.
• STT0 • SPT0 • MSTS0 • EXC0 • COI0 • TRC0 • ACKD0 • STD0
Do not cancel wait
Cancel wait. This setting is automatically cleared after wait is canceled.
LREL0
<6>
Figure 12-6. Format of IIC Control Register 0 (IICC0) (1/4)
2
C to operate (IICE0 = 1), set LREL0 (1) by using a 1-bit memory manipulation
WREL0
<5>
R/W
CHAPTER 12 SERIAL INTERFACE IIC0
User’s Manual U17854EJ9V0UD
SPIE0
<4>
WTIM0
Exit from communications
<3>
I
2
C operation enable
Wait cancellation
Condition for setting (IICE0 = 1)
• Set by instruction
Condition for setting (LREL0 = 1)
• Set by instruction
Condition for setting (WREL0 = 1)
• Set by instruction
Note 1
ACKE0
<2>
. Stop internal operation.
2
C is enabled to operate (IICE0 = 1)
STT0
<1>
SPT0
<0>
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