UPD78F1142AGB-GAH-AX Renesas Electronics America, UPD78F1142AGB-GAH-AX Datasheet - Page 841
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD78F1142AGB-GAH-AX
Manufacturer Part Number
UPD78F1142AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1142AGB-GAH-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1142AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 841 of 880
- Download datasheet (6Mb)
A/D
converter
Configuration
of serial
array unit
Registers
controlling
serial array
unit
Function
Input impedance
of ANI0 to ANI7
pins
AV
impedance
Interrupt request
flag (ADIF)
Conversion
results just after
A/D conversion
start
A/D conversion
result register
(ADCR,
ADCRH) read
operation
Starting the A/D
converter
SDRmn: Lower
8 bits of the
serial data
register mn
PER0:
Peripheral
enable register 0
SPSm: Serial
clock select
register m
REF
Details of
Function
pin input
This A/D converter charges a sampling capacitor for sampling during sampling time.
Therefore, only a leakage current flows when sampling is not in progress, and a
current that charges the capacitor flows during sampling. Consequently, the input
impedance fluctuates depending on whether sampling is in progress, and on the
other states.
To make sure that sampling is effective, however, it is recommended to keep the
output impedance of the analog input source to within 10 kΩ, and to connect a
capacitor of about 100 pF to the ANI0 to ANI7 pins (see Figure 10-26).
A series resistor string of several tens of kΩ is connected between the AV
AV
Therefore, if the output impedance of the reference voltage source is high, this will
result in a series connection to the series resistor string between the AV
pins, resulting in a large reference voltage error.
The interrupt request flag (ADIF) is not cleared even if the analog input channel
specification register (ADS) is changed.
Therefore, if an analog input pin is changed during A/D conversion, the A/D
conversion result and ADIF for the pre-change analog input may be set just before
the ADS rewrite. Caution is therefore required since, at this time, when ADIF is read
immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the
post-change analog input has not ended.
When A/D conversion is stopped and then resumed, clear ADIF before the A/D
conversion operation is resumed.
The first A/D conversion value immediately after A/D conversion starts may not fall
within the rating range if the ADCS bit is set to 1 within 1
set to 1. Take measures such as polling the A/D conversion end interrupt request
(INTAD) and removing the first conversion result.
When a write operation is performed to the A/D converter mode register (ADM),
analog input channel specification register (ADS), and A/D port configuration register
(ADPC), the contents of ADCR and ADCRH may become undefined. Read the
conversion result following conversion completion before writing to ADM, ADS, and
ADPC. Using a timing other than the above may cause an incorrect conversion
result to be read.
Start the A/D converter after the AV
Be sure to clear bit 8 to “0”.
When setting serial array unit m, be sure to set SAUmEN to 1 first. If SAUmEN = 0,
writing to a control register of serial array unit m is ignored, and, even if the register is
read, only the default value is read (except for input switch control register (ISC),
noise filter enable register (NFEN0), port input mode register (PIM0), port output
mode register (POM0), port mode registers (PM0, PM1), and port registers (P0, P1)).
After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
Be sure to clear bits 1 and 6 of PER0 register to 0.
Be sure to clear bits 15 to 8 to “0”.
After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
SS
pins.
APPENDIX B LIST OF CAUTIONS
User’s Manual U17854EJ9V0UD
REF
Cautions
voltage stabilize.
μ
s after the ADCE bit was
REF
and AV
REF
and
SS
p.340
p.342
p.342
p.342
p.343
p.343
p.330
p.330
p.331
p.331
p.331
p.332
839
(15/33)
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