UPD78F1142AGB-GAH-AX Renesas Electronics America, UPD78F1142AGB-GAH-AX Datasheet - Page 849
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD78F1142AGB-GAH-AX
Manufacturer Part Number
UPD78F1142AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1142AGB-GAH-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1142AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Standby
function
Reset
function
Power-on-
clear
circuit
Low-
voltage
detector
Function
STOP mode
Block diagram of
reset function
Watchdog timer
overflow
RESF: Reset
control flag
register
Timing of
generation of
internal reset
signal (LVIOFF =
1)
Timing of
generation of
internal reset
signal (LVIOFF =
0)
Cautions for
power-on-clear
circuit
LVIM: Low-
voltage
detection
register
Details of
Function
−
−
Input voltage from external input pin (EXLVI) must be EXLVI < V
To shorten oscillation stabilization time after the STOP mode is released when the
CPU operates with the high-speed system clock (X1 oscillation), temporarily switch
the CPU clock to the internal high-speed oscillation clock before the execution of the
STOP instruction. Before changing the CPU clock from the internal high-speed
oscillation clock to the high-speed system clock (X1 oscillation) after the STOP mode
is released, check the oscillation stabilization time with the oscillation stabilization
time counter status register (OSTC).
For an external reset, input a low level for 10
(If an external reset is effected upon power application, the period during which the
supply voltage is outside the operating range (V
μ
During reset input, the X1 clock, XT1 clock, internal high-speed oscillation clock, and
internal low-speed oscillation clock stop oscillating. External main system clock
input becomes invalid.
When the STOP mode is released by a reset, the RAM contents in the STOP mode
are held during reset input. However, because SFR and 2nd SFR are initialized, the
port pins become high-impedance, except for P130, which is set to low-level output.
An LVI circuit internal reset does not reset the LVI circuit.
A watchdog timer internal reset resets the watchdog timer.
Do not read data by a 1-bit memory manipulation instruction.
When the LVI default start function (bit 0 (LVIOFF) of 000C1H = 0) is used, LVIRF
flag may become 1 from the beginning depending on the power-on waveform.
If the low-voltage detector (LVI) is set to ON by an option byte by default, the reset
signal is not released until the supply voltage (V
If an internal reset signal is generated in the POC circuit, the reset control flag
register (RESF) is cleared to 00H.
Set the low-voltage detector by software after the reset status is released (see
CHAPTER 20 LOW-VOLTAGE DETECTOR).
Set the low-voltage detector by software after the reset status is released (see
CHAPTER 20 LOW-VOLTAGE DETECTOR).
In a system where the supply voltage (V
vicinity of the POC detection voltage (V
released from the reset status. In this case, the time from release of reset to the
start of the operation of the microcontroller can be arbitrarily set by taking the
following action.
To stop LVI, follow either of the procedures below.
• When using 8-bit memory manipulation instruction: Write 00H to LVIM.
• When using 1-bit memory manipulation instruction: Clear LVION to 0.
s. However, the low-level input may be continued before POC is released.)
APPENDIX B LIST OF CAUTIONS
User’s Manual U17854EJ9V0UD
Cautions
POC
), the system may be repeatedly reset and
DD
μ
) fluctuates for a certain period in the
s or more to the RESET pin.
DD
DD
) exceeds 2.07 V ±0.2 V.
< 1.8 V) is not counted in the 10
DD
.
p.616
p.610
p.615
p.615
p.615
p.617
p.623
p.623
pp.624,
625
p.624
p.626
p.627
p.628
p.633
p.633
847
Page
(23/33)
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