UPD78F1142AGB-GAH-AX Renesas Electronics America, UPD78F1142AGB-GAH-AX Datasheet - Page 364
UPD78F1142AGB-GAH-AX
Manufacturer Part Number
UPD78F1142AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1142AGB-GAH-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1142AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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362
Address: FFF20H
Address: FFF21H
(18) Port mode registers 0, 1 (PM0, PM1)
Symbol
Symbol
PM0
PM1
These registers set input/output of ports 0 and 1 in 1-bit units.
When using the P02/SO10/T
P13/T
PM13 bits to 0, and set the output latches of P02, P03, P04, P10, P12, and P13 to 1.
When using the P03/SI10/R
pins for serial data input or serial clock input, set the PM03, PM04, PM10, PM11, and PM14 bits to 1. At this
time, the output latches of P03, P04, P10, P11, and P14 may be 0 or 1.
PM0 and PM1 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
X
D3 pins for serial data output or serial clock output, clear the PM02, PM03, PM04, PM10, PM12, and
PMmn
PM17
0
1
7
1
7
After reset: FFH
After reset: FFH
Figure 11-21. Format of Port Mode Registers 0 and 1 (PM0, PM1)
Output mode (output buffer on)
Input mode (output buffer off)
PM06
PM16
6
6
R/W
R/W
X
X
D1, P03/SI10/R
D1/SDA10, P04/SCK10/SCL10, P10/SCK00, P11/SI00/R
CHAPTER 11 SERIAL ARRAY UNIT
PM05
PM15
5
5
User’s Manual U17854EJ9V0UD
Pmn pin I/O mode selection (m = 0, 1; n = 0 to 7)
X
D1/SDA10, P04/SCK10/SCL10, P10/SCK00, P12/SO00/T
PM04
PM14
4
4
PM03
PM13
3
3
PM02
PM12
2
2
PM01
PM11
X
1
1
D0, and P14/R
PM00
PM10
0
0
X
X
D0,
D3
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