UPD78F1142AGB-GAH-AX Renesas Electronics America, UPD78F1142AGB-GAH-AX Datasheet - Page 506
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UPD78F1142AGB-GAH-AX
Manufacturer Part Number
UPD78F1142AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1142AGB-GAH-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Company:
Part Number:
UPD78F1142AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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12.5.14 Wakeup function
and extension code have been received.
addresses do not match.
addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has
generated a start condition) to a slave device.
wakeup function, and this determines whether interrupt requests are enabled or disabled.
504
During address transmission
Read/write data after address transmission
During extension code transmission
Read/write data after extension code transmission
During data transmission
During ACK transfer period after data transmission
When restart condition is detected during data transfer
When stop condition is detected during data transfer
When data is at low level while attempting to generate a restart
condition
When stop condition is detected while attempting to generate a
restart condition
When data is at low level while attempting to generate a stop
condition
When SCL0 is at low level while attempting to generate a
restart condition
Notes 1. When WTIM0 (bit 3 of IIC control register 0 (IICC0)) = 1, an interrupt request occurs at the falling edge
Remark
The I
This function makes processing more efficient by preventing unnecessary INTIIC0 signal from occurring when
When a start condition is detected, wakeup standby mode is set. This wakeup standby mode is in effect while
However, when a stop condition is detected, bit 4 (SPIE0) of IIC control register 0 (IICC0) is set regardless of the
2
C bus slave function is a function that generates an interrupt request signal (INTIIC0) when a local address
2. When there is a chance that arbitration will occur, set SPIE0 = 1 for master device operation.
of the ninth clock. When WTIM0 = 0 and the extension code’s slave address is received, an interrupt
request occurs at the falling edge of the eighth clock.
SPIE0: Bit 4 of IIC control register 0 (IICC0)
Table 12-6. Status During Arbitration and Interrupt Request Generation Timing
Status During Arbitration
CHAPTER 12 SERIAL INTERFACE IIC0
User’s Manual U17854EJ9V0UD
At falling edge of eighth or ninth clock following byte transfer
When stop condition is generated (when SPIE0 = 1)
At falling edge of eighth or ninth clock following byte transfer
When stop condition is generated (when SPIE0 = 1)
At falling edge of eighth or ninth clock following byte transfer
Interrupt Request Generation Timing
Note 2
Note 2
Note 1
Note 1
Note 1
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