AT89C5122D-RDRIM Atmel, AT89C5122D-RDRIM Datasheet - Page 101
![IC MCU 80C51 W/SMART CARD 64VQFP](/photos/6/81/68127/313-64-vqfp_sml.jpg)
AT89C5122D-RDRIM
Manufacturer Part Number
AT89C5122D-RDRIM
Description
IC MCU 80C51 W/SMART CARD 64VQFP
Manufacturer
Atmel
Series
89Cr
Specifications of AT89C5122D-RDRIM
Core Processor
8051
Core Size
8-Bit
Speed
48MHz
Connectivity
SmartCard, SPI, UART/USART, USB
Peripherals
LED, POR, WDT
Number Of I /o
46
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-03 - KIT STARTER FOR MCU AT8XC5122/23
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
AT89C5122DRDRIMTR
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Bulk / Interrupt
Transactions
Bulk/Interrupt OUT
Transactions in Standard
Mode
4202F–SCR–07/2008
Bulk and Interrupt transactions are managed in the same way.
Figure 54. Bulk/Interrupt OUT transactions in Standard Mode
An endpoint should be first enabled and configured before being able to receive Bulk or
Interrupt packets.
When a valid OUT packet is received on an endpoint, the RXOUTB0 bit is set by the
USB controller. This triggers an interrupt if enabled. The firmware has to select the cor-
responding endpoint, store the number of data bytes by reading the UBYCTX register. If
the received packet is a ZLP (Zero Length Packet), the UBYCTX register value is equal
to 0 and no data has to be read.
When all the endpoint FIFO bytes have been read, the firmware should clear the
RXOUTB0 bit to allow the USB controller to accept the next OUT packet on this end-
point. Until the RXOUTB0 bit has been cleared by the firmware, the USB controller will
answer a NAK handshake for each OUT requests.
If the Host sends more bytes than supported by the endpoint FIFO, the overflow data
won’t be stored, but the USB controller will consider that the packet is valid if the CRC is
correct and the endpoint byte counter contains the number of bytes sent by the Host.
OUT
OUT
OUT
OUT
HOST
DATA1
DATA0 (n bytes)
DATA1
DATA1
AT83R5122, AT8xC5122/23
ACK
ACK
NAK
NAK
UFI
RXOUTB0
RXOUTB0
Endpoint FIFO read byte 1
Endpoint FIFO read byte 2
Endpoint FIFO read byte n
Endpoint FIFO read byte 1
Clear RXOUTB0
C51
101
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