AT89C5122D-RDRIM Atmel, AT89C5122D-RDRIM Datasheet - Page 84

IC MCU 80C51 W/SMART CARD 64VQFP

AT89C5122D-RDRIM

Manufacturer Part Number
AT89C5122D-RDRIM
Description
IC MCU 80C51 W/SMART CARD 64VQFP
Manufacturer
Atmel
Series
89Cr
Datasheets

Specifications of AT89C5122D-RDRIM

Core Processor
8051
Core Size
8-Bit
Speed
48MHz
Connectivity
SmartCard, SPI, UART/USART, USB
Peripherals
LED, POR, WDT
Number Of I /o
46
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-03 - KIT STARTER FOR MCU AT8XC5122/23
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
AT89C5122DRDRIMTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT89C5122D-RDRIM
Manufacturer:
Atmel
Quantity:
10 000
Table 53. Smart Card Transmit Guard Time Register 0 - SCGT0 (S:B4h, SCRS=1)
Reset Value = 0000 1100b
Table 54. Smart Card Transmit Guard Time Register 1 - SCGT1 (S:B5h, SCRS=1)
Reset Value = XXXX XXX0b
Table 55. Smart Card Character/Block Waiting Time Register 3
SCWT3 (S:C1h, SCRS=0)
Reset Value = 0000 0000b
84
Bit Number
Bit Number
Bit Number
WT31
7 - 0
7 - 1
7 - 0
GT7
7
7
7
0
-
AT83R5122, AT8xC5122/23
Bit Mnemonic
Bit Mnemonic
Bit Mnemonic
WT[31:24]
GT[7:0]
WT30
GT6
GT8
6
6
6
-
-
Description
Transmit Guard Time LSB
The minimum time between two consecutive start bits in transmit mode is GT[8:0] * ETU. This is equal to ISO IEC
Guard Time +10 (see Guard Time Counter description.
According to ISO IEC 7816,the time between 2 consecutive leading edge start bits can be set between 11 and
266 (11 to 254+12 ETUs).
Description
Reserved
The value read from these bits is indeterminate. Do not change these bits.
Transmit Guard Time MSB
Used together with the Transmit Guard Time LSB in SCGT0 register (Table 53).
Description
Waiting Time Byte3
Used together with WT[23:0] in registers SCWT2,SCWT1, SCWT0 (see Table 56).
WT29
GT5
5
5
5
-
WT28
GT4
4
4
4
-
WT27
GT3
3
3
3
-
WT26
GT2
2
2
2
-
WT25
GT1
1
1
1
-
4202F–SCR–07/2008
WT24
GT0
GT8
0
0
0

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