AT89C5122D-RDRIM Atmel, AT89C5122D-RDRIM Datasheet - Page 130

• Manufacturer Part Number: AT89C5122D-RDRIM
• Description: IC MCU 80C51 W/SMART CARD 64VQFP
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C5122D-RDRIM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: SmartCard, SPI, UART/USART, USB
• Peripherals: LED, POR, WDT
• Number Of I /o: 46
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-03 - KIT STARTER FOR MCU AT8XC5122/23
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: AT89C5122DRDRIMTR

Modes 2 and 3
Transmission
(Modes 1, 2 and 3)
Reception
(Modes 1, 2 and 3)
Framing Error Detection
(Modes 1, 2 and 3)
130
AT83R5122, AT8xC5122/23
Modes 2 and 3
Figure 75. Data Frame Format (Mode 1)
Modes 2 and 3 are full-duplex, asynchronous modes. The data frame (see Figure 76)
consists of 11 bits: one start bit, eight data bits (transmitted and received LSB first), one
programmable ninth data bit and one stop bit. Serial data is transmitted on the TXD pin
and received on the RXD pin. On receive, the ninth bit is read from RB8 bit in SCON
register. On transmit, the ninth data bit is written to TB8 bit in SCON register. Alterna-
tively, you can use the ninth bit as a command/data flag.
Figure 76. Data Frame Format (Modes 2 and 3)
To initiate a transmission, write to SCON register, setting SM0 and SM1 bits according
to Figure 69 on page 128, and setting the ninth bit by writing to TB8 bit. Then, writing the
byte to be transmitted to SBUF register starts the transmission.
To prepare for a reception, write to SCON register, setting SM0 and SM1 bits according
to Figure 69 on page 128, and setting REN bit. The actual reception is then initiated by a
detected high-to-low transition on the RXD pin.
Framing error detection is provided for the three asynchronous modes. To enable the
framing bit error detection feature, set SMOD0 bit in PCON register as shown in
Figure 77.
When this feature is enabled, the receiver checks each incoming data frame for a valid
stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous
transmission by two devices. If a valid stop bit is not found, the software sets FE bit in
SCON register.
Software may examine FE bit after each reception to check for data errors. Once set,
only software or a chip reset clear FE bit. Subsequently received frames with valid stop
bits cannot clear FE bit. When the framing error detection feature is enabled, RI rises on
stop bit instead of the last data bit as detailed in Figure 75 and Figure 76.
Figure 77. Framing Error Block Diagram
Mode 1
Framing Error
Controller
Start bit
Start bit
D0
FE
SM0
D0
D1
SMOD0
PCON.6
D1
D2
1
0
D2
D3
9-bit data
D3
SM0/FE
D4
SCON.7
8-bit data
D4
D5
D5
D6
D6
D7
D7
D8
4202F–SCR–07/2008
Stop bit
Stop bit