AT89C5122D-RDRIM Atmel, AT89C5122D-RDRIM Datasheet - Page 116
![IC MCU 80C51 W/SMART CARD 64VQFP](/photos/6/81/68127/313-64-vqfp_sml.jpg)
AT89C5122D-RDRIM
Manufacturer Part Number
AT89C5122D-RDRIM
Description
IC MCU 80C51 W/SMART CARD 64VQFP
Manufacturer
Atmel
Series
89Cr
Specifications of AT89C5122D-RDRIM
Core Processor
8051
Core Size
8-Bit
Speed
48MHz
Connectivity
SmartCard, SPI, UART/USART, USB
Peripherals
LED, POR, WDT
Number Of I /o
46
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-03 - KIT STARTER FOR MCU AT8XC5122/23
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
AT89C5122DRDRIMTR
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AT83R5122, AT8xC5122/23
Table 65. USB Global Interrupt Register - USBINT (S:BDh)
Reset Value = 0000 0000b
Bit Number
7 - 6
2-1
7
-
5
4
3
0
Mnemonic Description
WUPCPU
EORINT
SOFINT
SPINT
Bit
6
-
-
-
Reserved
The value read from these bits is always 0. Do not change these bits.
Wake-up CPU Interrupt
This bit is set by hardware when the USB controller is in SUSPEND state and is
re-activated by a non-idle signal FROM USB line (not by an upstream resume).
This triggers a USB interrupt when EWUPCPU is set in the Table on page 117.
When receiving this interrupt, user has to enable all USB clock inputs.
This bit should be cleared by software (USB clocks must be enabled before).
End of Reset Interrupt
This bit is set by hardware when End of Reset has been detected by the USB
controller. This triggers a USB interrupt when EEORINT is set in the Table on
page 117.
This bit should be cleared by software.
Start Of Frame Interrupt
This bit is set by hardware when an USB Start Of Frame PID (SOF) has been
detected. This triggers a USB interrupt when ESOFINT is set in the Table on
page 117.
This bit should be cleared by software.
Reserved
The value read from these bits is always 0. Do not change these bits.
Suspend Interrupt
This bit is set by hardware when a USB Suspend (Idle bus for three frame
periods: a J state for 3 ms) is detected. This triggers a USB interrupt when
ESPINT is set in USBIEN register (Table 66 on page 117).
This bit must be cleared by software before powering the microcontroller down
as it disables the USB pads to reduce the power consumption.
WUPCPU
5
EORINT
4
SOFINT
3
2
-
1
-
4202F–SCR–07/2008
SPINT
0
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