ATMEGA323-8AI Atmel, ATMEGA323-8AI Datasheet - Page 163
![IC AVR MCU 32K 8MHZ IND 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA323-8AI
Manufacturer Part Number
ATMEGA323-8AI
Description
IC AVR MCU 32K 8MHZ IND 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA323L-4PC.pdf
(247 pages)
Specifications of ATMEGA323-8AI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA3238AI
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Using the JTAG
Programming
Capabilities
Bibliography
1457G–AVR–09/03
Programming of AVR parts via JTAG is performed via the 4-pin JTAG port, TCK, TMS,
TDI and TDO. These are the only pins that need to be controlled/observed to perform
JTAG programming (in addition to power pins). It is not required to apply 12V externally.
The JTAGEN Fuse must be programmed and the JTD bit in the MCUSR Register must
be cleared to enable the JTAG Test Access Port.
The JTAG programming capability supports:
•
•
•
•
The lock bit security is exactly as in parallel programming mode. If the Lock bits LB1 or
LB2 are programmed, the OCDEN Fuse cannot be programmed unless first doing a
chip erase. This is a security feature that ensures no back-door exists for reading out the
content of a secured device.
A description of the programming specific JTAG instructions is given in “Programming
specific JTAG instructions” on page 202. The details on programming through the JTAG
interface is given in the section “Programming via the JTAG Interface” on page 202
For more information about general Boundary-Scan, the following literature can be
consulted:
•
•
Flash programming and verifying
EEPROM programming and verifying
Fuse programming and verifying
Lock bit programming and verifying
IEEE: IEEE Std 1149.1-1990. IEEE Standard Test Access Port and Boundary-Scan
Architecture, IEEE, 1993
Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison-
Wesley, 1992
ATmega323(L)
163
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