ATMEGA323-8AI Atmel, ATMEGA323-8AI Datasheet - Page 77
![IC AVR MCU 32K 8MHZ IND 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA323-8AI
Manufacturer Part Number
ATMEGA323-8AI
Description
IC AVR MCU 32K 8MHZ IND 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA323L-4PC.pdf
(247 pages)
Specifications of ATMEGA323-8AI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA3238AI
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Double Speed Operation
(U2X)
External Clock
Synchronous Clock Operation When synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock
1457G–AVR–09/03
Table 29 contains equations for calculating the baud rate (in bits per second) and for
calculating the UBRR value for each mode of operation using an internally generated
clock source.
Table 29. Equations for Calculating Baud Rate Register Setting
Note:
The transfer rate can be doubled by setting the U2X bit in UCSRA. Setting this bit only
has effect for the asynchronous operation. Set this bit to zero when using synchronous
operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively
doubling the transfer rate for asynchronous communication. Note however that the
Receiver will in this case only use half the number of samples (reduced from 16 to 8) for
data sampling and clock recovery, and therefore a more accurate baud rate setting and
system clock are required when this mode is used. For the Transmitter, there are no
downsides.
External clocking is used by the Synchronous Slave modes of operation. The descrip-
tion in this section refers to Figure 46 for details.
External clock input from the XCK pin is sampled by a synchronization register to mini-
mize the chance of meta-stability. The output from the synchronization register must
then pass through an edge detector before it can be used by the Transmitter and
Receiver. This process introduces a two CPU clock period delay and therefore the max-
imum external XCK clock frequency is limited by the following equation:
Note that f
mended to add some margin to avoid possible loss of data due to frequency variations.
input (Slave) or clock output (Master). The dependency between the clock edges and
data sampling or data change is the same. The basic principle is that data input (on
RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is
changed.
Operating Mode
Asynchronous Normal Mode
(U2X = 0)
Asynchronous Double Speed
Mode (U2X = 1)
Synchronous Master Mode
1. The baud rate is defined to be the transfer rate in bit per second (bps).
osc
BAUD
f
UBRR
Some examples of UBRR values for some system clock frequency are found in Table
36 (see page 99).
OSC
depends on the stability of the system clock source. It is therefore recom-
System Oscillator clock frequency
Contents of the UBRRH and UBRRL Registers, (0 - 4095)
Baud rate (in bits per second, bps)
BAUD
BAUD
BAUD
Equation for Calculating
f
XCK
Baud Rate
=
=
=
--------------------------------------- -
16 UBRR
----------------------------------- -
8 UBRR
----------------------------------- -
2 UBRR
f
---------- -
OSC
4
f
f
f
OSC
OSC
OSC
(1)
+
+
+
1
1
1
ATmega323(L)
Equation for Calculating
UBRR
UBRR
UBRR
UBRR Value
=
=
=
----------------------- - 1
16BAUD
-------------------- - 1
8BAUD
-------------------- - 1
2BAUD
f
f
f
OSC
OSC
OSC
–
–
–
77
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