ATMEGA323-8AI Atmel, ATMEGA323-8AI Datasheet - Page 87
![IC AVR MCU 32K 8MHZ IND 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA323-8AI
Manufacturer Part Number
ATMEGA323-8AI
Description
IC AVR MCU 32K 8MHZ IND 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA323L-4PC.pdf
(247 pages)
Specifications of ATMEGA323-8AI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA3238AI
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Parity Checker
Disabling the Receiver
Flushing the Receive Buffer
1457G–AVR–09/03
The parity checker is active when the high USART Parity Mode (UPM1) bit is set. Type
of parity check to be performed (odd or even) is selected by the UPM0 bit. When
enabled, the parity checker calculates the parity of the data bits in incoming frames and
compares the result with the parity bit from the serial frame. The result of the check is
stored in the receive buffer together with the received data and stop bits. The Parity
Error (PE) Flag can then be read by software to check if the frame had a parity error.
The PE bit is set if the next character that can be read from the receive buffer had a par-
ity error when received and the parity checking was enabled at that point (UPM1 = 1).
This bit is valid until the receive buffer (UDR) is read.
In contrast to the Transmitter, disabling the of the Receiver will be immediate. Data from
ongoing receptions will therefore be lost. When disabled (i.e. the RXEN is set to zero)
the Receiver will no longer override the normal function of the RxD port pin. The
Receiver Buffer FIFO will be flushed when the Receiver is disabled. Remaining data in
the buffer will be lost
The Receiver Buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer
will be emptied of its contents. Unread data will be lost. If the buffer has to be flushed
during normal operation, due to for instance an error condition, read the UDR I/O loca-
tion until the RXC Flag is cleared. The following code example shows how to flush the
receive buffer.
Note:
Assembly Code Example
C Code Example
USART_Flush:
void USART_Flush( void )
{
}
sbis UCSRA, RXC
ret
in
rjmp USART_Flush
unsigned char dummy;
while ( UCSRA & (1<<RXC) ) dummy = UDR;
1. The example code assumes that the part specific header file is included.
r16, UDR
(1)
(1)
ATmega323(L)
87
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