ATMEGA323-8AI Atmel, ATMEGA323-8AI Datasheet - Page 168
![IC AVR MCU 32K 8MHZ IND 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA323-8AI
Manufacturer Part Number
ATMEGA323-8AI
Description
IC AVR MCU 32K 8MHZ IND 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA323L-4PC.pdf
(247 pages)
Specifications of ATMEGA323-8AI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA3238AI
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Boundary-Scan Chain
Scanning the Digital Port Pins
168
ATmega323(L)
The Boundary-Scan chain has the capability of driving and observing the logic levels on
the digital I/O pins.
Note:
Figure 89 shows the Boundary-Scan Cell for Bidirectional Port Pins with Pull-up func-
tion. The cell consists of a standard Boundary-Scan cell for the Pull-up function, and a
Bidirectional pin cell that combines the three signals Output Control – OC, Output Data
– OD, and Input Data – ID, into only a two-stage Shift Register.
Figure 89. Boundary-Scan Cell For bidirectional Port Pin with Pull-up Function.
The Boundary-Scan logic is not included in the figures in the datasheet. Figure 90
shows a simple digital Port Pin as described in the section “I/O Ports” on page 137. The
Boundary-Scan details from Figure 89 replaces the dashed box in Figure 90.
Pullup Disable (PLD)
Output Control (OC)
Output Data (OD)
Input Data (ID)
Compatibility issues regarding future devices: Future devices, included replacements for
ATmega323 will have Pull-Up Enable signals instead of the Pull-Up Disable signals in the
scan path (i.e. inverted logic). The scan cell for the reset signal will have the same logic
level as the external pin (i.e. inverted logic). The length of the scan-chain is likely to
change in future devices.
0
1
From Last Cell
0
1
0
1
0
1
ShiftDR
ClockDR
D
D
D
FF2
FF1
FF0
To Next Cell
Q
Q
Q
UpdateDR
D
G
D
G
D
G
LD2
LD1
LD0
Q
Q
Q
0
1
0
1
0
1
EXTEST
1457G–AVR–09/03
Vcc
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