ATMEGA8535L-8AC Atmel, ATMEGA8535L-8AC Datasheet - Page 108

• Manufacturer Part Number: ATMEGA8535L-8AC
• Description: IC AVR MCU 8K LV 8MHZ COM 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8535L-8AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Timer/Counter Timing
Diagrams
108
ATmega8535(L)
In phase and frequency correct PWM mode, the compare units allow generation of
PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a
non-inverted PWM and an inverted PWM output can be generated by setting the
COM1x1:0 to three (see Table 47 on page 111). The actual OC1x value will only be vis-
ible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The
PWM waveform is generated by setting (or clearing) the OC1x Register at the Compare
Match between OCR1x and TCNT1 when the counter increments, and clearing (or set-
ting) the OC1x Register at Compare Match between OCR1x and TCNT1 when the
counter decrements. The PWM frequency for the output when using phase and fre-
quency correct PWM can be calculated by the following equation:
The “N” variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represents special cases when generating
a PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to
BOTTOM the output will be continuously low and if set equal to TOP, the output will be
set to high for non-inverted PWM mode. For inverted PWM, the output will have the
opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 9) and
COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle.
The Timer/Counter is a synchronous design and the timer clock (clk
shown as a clock enable signal in the following figures. The figures include information
on when interrupt flags are set, and when the OCR1x Register is updated with the
OCR1x buffer value (only for modes utilizing double buffering). Figure 49 shows a timing
diagram for the setting of OCF1x.
Figure 49. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling
Figure 50 shows the same timing data, but with the prescaler enabled.
TCNTn
OCRnx
OCFnx
(clk
clk
clk
I/O
I/O
Tn
/1)
OCRnx - 1
f
OCnxPFCPWM
OCRnx
OCRnx Value
=
--------------------------- -
2 N TOP
⋅
f
clk_I/O
⋅
OCRnx + 1
T1
) is therefore
2502K–AVR–10/06
OCRnx + 2