ATMEGA8535L-8AC Atmel, ATMEGA8535L-8AC Datasheet - Page 177

• Manufacturer Part Number: ATMEGA8535L-8AC
• Description: IC AVR MCU 8K LV 8MHZ COM 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8535L-8AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Combining Address and Data
Packets into a Transmission
Multi-master Bus
Systems, Arbitration and
Synchronization
2502K–AVR–10/06
Figure 80. Data Packet Format
A transmission basically consists of a START condition, a SLA+R/W, one or more data
packets and a STOP condition. An empty message, consisting of a START followed by
a STOP condition is illegal. Note that the wired-ANDing of the SCL line can be used to
implement handshaking between the Master and the Slave. The Slave can extend the
SCL low period by pulling the SCL line low. This is useful if the clock speed set up by the
Master is too fast for the Slave or the Slave needs extra time for processing between the
data transmissions. The Slave extending the SCL low period will not affect the SCL high
period, which is determined by the Master. As a consequence, the Slave can reduce the
TWI data transfer speed by prolonging the SCL duty cycle.
Figure 81 shows a typical data transmission. Note that several data bytes can be trans-
mitted between the SLA+R/W and the STOP condition, depending on the software
protocol implemented by the application software.
Figure 81. Typical Data Transmission
The TWI protocol allows bus systems with several masters. Special concerns have
been taken in order to ensure that transmissions will proceed as normal, even if two or
more masters initiate a transmission at the same time. Two problems arise in multi-mas-
ter systems:
•
•
The wired-ANDing of the bus lines is used to solve both these problems. The serial
clocks from all Masters will be wired-ANDed, yielding a combined clock with a high
Transmitter
SDA
SCL
Aggregate
SDA From
SDA From
SCL From
Receiver
Master
SDA
An algorithm must be implemented allowing only one of the Masters to complete the
transmission. All other masters should cease transmission when they discover that
they have lost the selection process. This selection process is called arbitration.
When a contending Master discovers that it has lost the arbitration process, it
should immediately switch to Slave mode to check whether it is being addressed by
the winning Master. The fact that multiple masters have started transmission at the
same time should not be detectable to the slaves, i.e., the data being transferred on
the bus must not be corrupted.
Different Masters may use different SCL frequencies. A scheme must be devised to
synchronize the serial clocks from all Masters, in order to let the transmission
proceed in a lockstep fashion. This will facilitate the arbitration process.
START
SLA+R/W
Addr MSB
1
2
Data MSB
SLA+R/W
1
Addr LSB
7
2
R/W
8
ACK
9
Data Byte
7
Data MSB
Data LSB
1
8
2
Data Byte
ATmega8535(L)
ACK
9
7
Data LSB
8
STOP, REPEATED
ACK
9
START or Next
Data Byte
STOP
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