ATMEGA8535L-8AC Atmel, ATMEGA8535L-8AC Datasheet - Page 131

• Manufacturer Part Number: ATMEGA8535L-8AC
• Description: IC AVR MCU 8K LV 8MHZ COM 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8535L-8AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Output Compare Register –
OCR2
Asynchronous Operation
of the Timer/Counter
Asynchronous Status
Register – ASSR
2502K–AVR–10/06
The Output Compare Register contains an 8-bit value that is continuously compared
with the counter value (TCNT2). A match can be used to generate an output compare
interrupt, or to generate a waveform output on the OC2 pin.
• Bit 3 – AS2: Asynchronous Timer/Counter2
When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clk
AS2 is written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to
the Timer Oscillator1 (TOSC1) pin. When the value of AS2 is changed, the contents of
TCNT2, OCR2, and TCCR2 might be corrupted.
• Bit 2 – TCN2UB: Timer/Counter2 Update Busy
When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes
set. When TCNT2 has been updated from the temporary storage register, this bit is
cleared by hardware. A logical zero in this bit indicates that TCNT2 is ready to be
updated with a new value.
• Bit 1 – OCR2UB: Output Compare Register 2 Update Busy
When Timer/Counter2 operates asynchronously and OCR2 is written, this bit becomes
set. When OCR2 has been updated from the temporary storage register, this bit is
cleared by hardware. A logical zero in this bit indicates that OCR2 is ready to be
updated with a new value.
• Bit 0 – TCR2UB: Timer/Counter Control Register 2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2 is written, this bit becomes
set. When TCCR2 has been updated from the temporary storage register, this bit is
cleared by hardware. A logical zero in this bit indicates that TCCR2 is ready to be
updated with a new value.
If a write is performed to any of the three Timer/Counter2 Registers while its update
busy flag is set, the updated value might get corrupted and cause an unintentional inter-
rupt to occur.
The mechanisms for reading TCNT2, OCR2, and TCCR2 are different. When reading
TCNT2, the actual timer value is read. When reading OCR2 or TCCR2, the value in the
temporary storage register is read.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
R/W
R
7
–
0
7
0
R
6
–
0
R/W
6
0
R
5
–
0
R/W
5
0
R
4
–
0
R/W
4
0
OCR2[7:0]
AS2
R/W
3
0
R/W
3
0
TCN2UB
R
2
0
R/W
2
0
ATmega8535(L)
OCR2UB
R
1
0
R/W
1
0
TCR2UB
R/W
R
0
0
0
0
I/O
ASSR
. When
OCR2
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