ADUC831BS Analog Devices Inc, ADUC831BS Datasheet - Page 21

IC ADC/DAC 12BIT W/MCU 52-MQFP

ADUC831BS

Manufacturer Part Number
ADUC831BS
Description
IC ADC/DAC 12BIT W/MCU 52-MQFP
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC8xxr
Datasheet

Specifications of ADUC831BS

Rohs Status
RoHS non-compliant
Core Processor
8052
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
PSM, Temp Sensor, WDT
Number Of I /o
34
Program Memory Size
62KB (62K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
52-MQFP, 52-PQFP
For Use With
EVAL-ADUC831QSZ - KIT DEV FOR ADUC831 QUICK START

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ADCCON3 – (ADC Control SFR #3)
The ADCCON3 register controls the operation of various calibra-
tion modes as well as giving an indication of ADC busy status.
SFR Address:
SFR Power-On Default Value:
Bit Addressable:
Bit
ADCCON3.7 BUSY
ADCCON3.6 GNCLD
ADCCON3.5 AVGS1
ADCCON3.4 AVGS0
ADCCON3.3 RSVD
ADCCON3.2 RSVD
ADCCON3.1 TYPICAL
ADCCON3.0 SCAL
REV. 0
Name
Description
The ADC Busy Status Bit (BUSY) is a read-only status bit that is set during a valid ADC conversion or
calibration cycle. Busy is automatically cleared by the core at the end of conversion or calibration.
Gain Calibration Disable Bit
Set to “0” to Enable Gain Calibration.
Set to “1” to Disable Gain Calibration.
Number of Averages Selection Bits
This bit selects the number of ADC readings averaged during a calibration cycle.
AVGS1
0
0
1
1
Reserved. This bit should always be written as “0.”
This bit should always be written as “1” by the user when performing calibration.
Calibration Type Select Bit.
This bit selects between Offset (zero-scale) and gain (full-scale) calibration.
Set to 0 for Offset Calibration.
Set to 1 for Gain Calibration.
Start Calibration Cycle Bit.
When set, this bit starts the selected calibration cycle. It is automatically cleared when the calibration
cycle is completed.
F5H
00H
NO
AVGS0
0
1
0
1
Table V. ADCCON3 SFR Bit Designations
Number of Averages
15
1
31
63
–21–
ADuC831

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