W90N740CDG Nuvoton Technology Corporation of America, W90N740CDG Datasheet
W90N740CDG
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W90N740CDG Summary of contents
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... W90N740CD/W90N740CDG 32-BIT ARM7TDMI-BASED MICRO-CONTROLLER The information described in this document is the exclusive intellectual property of Winbond Electronics Corporation and shall not be reproduced without permission from Winbond. Winbond is providing this document only for reference purposes of W90N740-based system design. Winbond assumes no responsibility for errors or omissions. ...
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... Ethernet MAC Controller (EMC) ................................................................................... 64 7.5.1 EMC Descriptors ............................................................................................................64 7.5.2 EMC Register Mapping ..................................................................................................70 7.6 Network Address Translation Accelerator (NATA) ..................................................... 101 7.6.1 NAT Process Flow........................................................................................................102 7.6.2 NATA Registers Map....................................................................................................103 7.7 GDMA Controller ........................................................................................................ 113 7.7.1 GDMA Function Description .........................................................................................113 7.7.2 GDMA Registers Map...................................................................................................114 W90N740CD/W90N740CDG - II - ...
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... EBI/External Master Interface AC Characteristics ........................................................176 8.3.3 EBI/(ROM/SRAM/External I/O) AC Characteristics ......................................................177 8.3.4 USB Transceiver AC Characteristics............................................................................178 8.3.5 EMC MII AC Characteristics .........................................................................................179 9. PACKAGE DIMENSIONS ....................................................................................................... 181 10. W90N740 REGISTERS MAPPING TABLE ............................................................................ 182 11. ORDERING INFORMATION .................................................................................................. 194 12. REVISION HISTORY .............................................................................................................. 194 W90N740CD/W90N740CDG Publication Release Date: Aug. 18, 2005 - III - Revision A6 ...
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... The data bus width of external memory address & data bus connection with external memory • Bus arbitration supports the Fixed Priority Mode & Rotate Priority Mode • Power-On setting • On-Chip PLL module control & Clock select control W90N740CD/W90N740CDG Publication Release Date: Aug. 18, 2005 - 1 - Revision A6 ...
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... Support TCP / UDP packets GDMA Controller • 2 Channel GDMA for memory-to-memory data transfers without CPU intervention • Increase or decrease source / destination address in 8-bit, 16-bit, or 32-bit data transfers • Supports 4-data burst mode to boost performance • Support external GDMA request W90N740CD/W90N740CDG - 2 - ...
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... Programmable as either low-active or high-active for 4 external interrupt sources • Priority methodology is encoded to allow for interrupt daisy-chaining • Automatically mask out the lower priority interrupt during interrupt nesting GPIO Controller • Programmable as an input or output pin W90N740CD/W90N740CDG Publication Release Date: Aug. 18, 2005 - 3 - Revision A6 ...
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... Programmable clock frequency, and the input frequency range is 3-30MHz; 15MHz is preferred. Operation Voltage Range • 2.7 – 3.6 V for IO Buffer • 1.62 – 1.98 V for Core Logic Operation Temperature Range • 0 – 70 Degree C Operating Frequency • 80 MHz (default) Package Type • 176-pin LQFP W90N740CD/W90N740CDG - 4 - ...
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... JTAG ARM7TDMI ICE PLL SDRAM EBI Bus External Bus ROM Flash RAM PCMCIA IO Dev USB Device Ethenet MAC Controller 0 PHY W90N740CD/W90N740CDG TDMI Bus 8K-Byte Wrapper I Cache Clock AHB Controller Arbiter AHB APB Decoder Bridge Controller GDMA Controller USB Host Controller Ethenet ...
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... GP15/nXDACK GP16/nXDREQ 30 EMACK EMREQ nWAIT VDD33 nOE VSS33 35 nECS0 nECS1 nECS2 nECS3 40 nBTCS nSCS0 nSCS1 SDQM0 SDQM1 50 W90N740CD/W90N740CDG 165 160 155 150 W90N740 176-Pin LQFP Fig 4.1 176-Pin LQFP Pin Diagram - 6 - 145 140 135 USBVDD DP DN 130 USBVSS GP9/nDSR GP8/nDTR ...
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... External Bus Interface A [24:22] A [21:0] D [31:16] D [15:0] nWBE [3:0]/ SDQM [3:0] nSCS[1:0] NSRAS NSCAS NSWE MCKE NC NC EMREQ EMACK nWAIT NBTCS nECS[3:0] NOE W90N740CD/W90N740CDG 176-PIN LQFP ( 4 pins ) 164 163 pins ) pins ) 84-82 81-74, 72, 70,67-56 124-119, 117, 115-114, 111-105 104-103, 101, 99-88, 86 ...
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... RX0_DV / R0_CRSDV RX0_ERR Ethernet Interface (1) MDC1 MDIO1 COL1 CRS1 TX1_CLK TX1D [3:0] / R1A_TX [1:0] TX1_EN /R1A_TXEN RX1_CLK / R1A_REFCLK RX1D [3:0] / R1A_RXD [1:0] RX1_DV / R1A_CRSDV RX1_ERR / R1A_RXERR W90N740CD/W90N740CDG 176-PIN LQFP ( 17 pins ) 142 143 151 152 150 149-146 144 153 159-157, 154 160 161 ...
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... GP10 /TxD GP9/nDSR/nTOE GP8 /nDTR/FSE0 GP7 /nCD / VO GP6 /nCTS/ VM GP5 /nRTS/ VP GP4 /nRI / RCV GP [3:0] Power/Ground VDD18 VSS18 VDD33 VSS33 USBVDD USBVSS DVDD18 DVSS18 AVDD18 AVSS18 W90N740CD/W90N740CDG 176-PIN LQFP ( 2 pins ) 131 130 ( 21 pins ) 136-133 140 139 128 127 126 138 137 ...
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... EMREQ ID internal pull-down EMACK O nWAIT IU internal pull-up nBTCS O nECS [3:0] IO nOE O W90N740CD/W90N740CDG PAD TYPE - External Clock / Crystal Input - Crystal Output - System Master Clock Out, SDRAM clock - System Reset, active-low JTAG Test Clock, JTAG Test Mode Select, JTAG Test Data in, - JTAG Test Data out ...
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... I --, R0_RXD [1:0] RX0_DV / I R0_CRSDV RX0_ERR I W90N740CD/W90N740CDG DESCRIPTION MII Management Data Clock for Ethernet the reference - clock of MDIO0. Each MDIO0 data will be latched at the rising edge of MDC0 clock. MII Management Data I/O for Ethernet used to transfer MII - control and status information between PHY and MAC. ...
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... R1A_RXD[1:0] RX1_DV/ I R1A_CRSDV RX1_ERR / I R1A_RXERR W90N740CD/W90N740CDG PAD TYPE MII Management Data Clock for Ethernet the reference - clock of MDIO1. Each MDIO1 data will be latched at the rising edge of MDC1 clock. MII Management Data I/O for Ethernet used to transfer - MII control and status information between PHY and MAC. ...
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... USBVDD P USBVSS G DVDD18 P DVSS18 G AVDD18 P AVSS18 G W90N740CD/W90N740CDG DESCRIPTION - Differential Positive USB IO signal Differential Negative (Minus) USB IO signal - - External Interrupt Request or General Purpose I/O External DMA Request or General Purpose I External DMA Acknowledge or General Purpose I/O Timer 1 or General Purpose I/O. This pin is also used as SPEED, ...
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... A[31:0] Address Register Incrementer Register Bank (31 x 32-bit registers) (6 status registers Multiplier Barrel Shifter 32-bit ALU W90N740CD/W90N740CDG Address Instruction Decoder Instruction Pipeline Read Data Register Thumb Instruction Decoder Writer Data Register Fig 7.1 ARM7TDMI CPU Core Block Diagram - 14 - ...
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... In the event of an access request to an address outside any programmed bank size, an abort signal is generated. The maximum accessible memory size of each external IO bank is 32M bytes, and 64M bytes on SDRAM banks. W90N740CD/W90N740CDG Publication Release Date: Aug. 18, 2005 - 15 - Revision A6 ...
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... External I/O Bank 1 256KB - 32MB EBI Space External I/O Bank 0 256KB - 32MB SDRAM Bank 1 2MB - 64MB SDRAM Bank 0 2MB - 64MB ROM/FLASH 256KB - 32MB 0x0000.0000 W90N740CD/W90N740CDG Non-Cacheable space 0xFFFF.FFFF 512KB (Fixed) 0xFFF8.0000 512KB (Fixed) 0xFFF0.0000 10KB 0xFFE0.0000 EBI Space 0x8000.0000 Fig7 ...
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... The maximum accessible memory size of each external IO bank is 32M bytes . Table 7.2.2 Address Bus Generation Guidelines DATA BUS EXTERNAL ADDRESS PINS WIDTH A [22:0] A22 – A0 (Internal) 8-BIT A23 – A1 (Internal) 16-BIT A24 – A2 (Internal) 32-BIT W90N740CD/W90N740CDG DESCRIPTION AHB PERIPHERALS APB Peripherals A23 A24 A23 (Internal) A24 (Internal) A24 (Internal Publication Release Date: Aug ...
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... A and A+2, and the bytes at addresses A, A+1, A+2, and A+3 map on to each other when LITTLE pin is High Half-word at address A+2 Byte at address A+3 Byte at address A+2 Fig. 7.2.3 Little endian addresses of bytes and half-words within words W90N740CD/W90N740CDG Word at address A Half-word at address A+2 Byte at address A+2 Word at address A Half-word at address A Byte at address A+1 ...
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... Table7.2.14) show the program/data path between CPU register and the external memory using little / big endian and word/half-word/byte access. Fig. 7.2.4 Address/Data bus connection with external memory Fig. 7.2.5 CPU register Read/Write with external memory W90N740CD/W90N740CDG Publication Release Date: Aug. 18, 2005 - 19 - Revision A6 ...
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... CPU REG DATA SA WA BIT NUMBER 31 0 ABCD SD BIT NUMBER 31 0 ABCD NWBE [3-0] / AAAA SDQM [3-0] BIT NUMBER 31 0 ABCD XD BIT NUMBER 31 0 ABCD EXT. MEM DATA TIMING SEQUENCE W90N740CD/W90N740CDG X = Don’t care HALF WORD 31 0 ABCD WA+2 WA XXAA XXAA XXXA ...
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... Ext. Mem Data Timing Sequence Table 7.2.5 and Table 7.2.6 Using big-endian and half-word access, Program/Data path between register and external memory Address whose LSB HAU = Address whose LSB nWBE [3-0] / SDQM [3- means active and U means inactive W90N740CD/W90N740CDG HALF WORD 31 0 CDAB ...
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... Table7.2.6 Half-word access read operation with Big Endian ACCESS OPERATION XD WIDTH BIT NUMBER CPU REG DATA SA HAL BIT NUMBER BIT NUMBER HAL SDQM [3-0] AAUU BIT NUMBER BIT NUMBER EXT. MEM DATA TIMING SEQUENCE W90N740CD/W90N740CDG WORD HALF WORD ABCD ABCD HAU HAL HA UUAA XXAA 0 31 ...
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... Bit Number CPU Reg Data SA BA0 Bit Number Bit Number BA0 nWBE [3-0] / AUUU SDQM [3-0] Bit Number Bit Number Ext. Mem Data Timing Sequence W90N740CD/W90N740CDG BAU = Address whose LSB WORD 31 0 ABCD BA1 BA2 BA3 BA0 BA0 BA0 UAUU UUAU ...
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... ABCD XD BIT NUMBER EXT. MEM DATA TIMING SEQUENCE Table 7.2.9 and Table 7.2.10 Using little-endian and word access, Program/Data path between register and external memory WA = Address whose LSB nWBE [3-0] / SDQM [3- means active and U means inactive W90N740CD/W90N740CDG WORD BA1 BA2 BA3 ...
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... ABCD CPU REG DATA SA WA BIT NUMBER 31 0 ABCD SD BIT NUMBER 31 0 ABCD SDQM [3-0] AAAA BIT NUMBER 31 0 ABCD XD BIT NUMBER 31 0 ABCD EXT. MEM DATA TIMING 1st read SEQUENCE W90N740CD/W90N740CDG HALF WORD 31 0 ABCD WA+2 WA XXAA XXAA XXXA ...
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... CPU REG DATA CD HAL SA BIT NUMBER BIT NUMBER HAL SDQM [3-0] UUAA BIT NUMBER BIT NUMBER EXT. MEM DATA TIMING SEQUENCE W90N740CD/W90N740CDG HAL = Address whose LSB is 0,4,8 Don’t care WRITE OPERATION (CPU REGISTER WORD HALF WORD ABCD ABCD HAU ...
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... BIT NUMBER CPU REG DATA SA BA0 BIT NUMBER BIT NUMBER BA0 NWBE [3-0] / UUUA SDQM [3-0] BIT NUMBER BIT NUMBER EXT. MEM DATA TIMING SEQUENCE W90N740CD/W90N740CDG BAU = Address whose LSB WORD 31 0 ABCD BA1 BA2 BA3 BA0 BA0 BA0 UUAU UAUU ...
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... If IPEN bit is set to “1” and if no unmasked interrupt request, then the ARM Core’s priority is still lowest and the IPACT = 0, Bit 23 of the Arbitration Control Register (ARBCON) ； If there is an unmasked interrupt request, then the ARM Core’s priority is raised to second and IPACT = 1. W90N740CD/W90N740CDG WORD 7 0 ...
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... If pin D15 is pull-up, the PLL output clock is used as internal system clock. D14 pin：Little/Big Endian Mode Select If pin D14 is pull-down, the external memory format is Big Endian mode. If pin D14 is pull-up, the external memory format is Little Endian mode. W90N740CD/W90N740CDG FUNCTION BLOCK IPACT = 0 External Bus Master ...
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... This register is for read only and enables software to recognize certain characteristics of the chip ID and the version number. REGISTER ADDRESS PDID 0xFFF0.0000 31 30 PACKAGE W90N740CD/W90N740CDG Pull-down Pull-up Pull-down Pull-up W90N740 normal operation D [9:8] R/W DESCRIPTION R Product Identifier Register R/W Arbitration Control Register R/W PLL Control Register ...
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... IPEN [1] ： Interrupt priority enable bit 0 = the ARM core has the lowest priority enable to raise the ARM core priority to second This bit is available only when the PRTMOD = 0. PRTMOD [0] ： Priority mode select 0 = Fixed Priority Mode (default Rotate Priority Mode W90N740CD/W90N740CDG 1 R/W DESCRIPTION R/W Arbitration Control Register 28 ...
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... Feedback Divider divides the output clock from VCO of PLL. OTDV [6:5] ：PLL output clock divider OTDV [6: INDV [4:0] ：PLL input clock divider Input Divider divides the input reference clock into the PLL. W90N740CD/W90N740CDG R/W DESCRIPTION R/W PLL Control Register 28 27 RESERVED 20 ...
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... Clock Select Register (CLKSEL) REGISTER ADDRESS CLKSEL 0xFFF0.000C USBCKS RESERVED GDMA 7 6 USB TIMER UART W90N740CD/W90N740CDG PLL Output 480MHz Charge VCO Divider Pump FOUT (NO) OTDV[1:0] Fig 7.2.6 System PLL block diagram R/W DESCRIPTION R/W Clock Select Register 28 27 RESERVED 20 19 RESERVED ...
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... Enable WDT counting clock USB [7] ： USB clock enable bit 0 = Disable USB clock 1 = Enable USB clock TIMER [6] ： Timer clock enable bit 0 = Disable Timer clock 1 = Enable Timer clock UART [5] ： UART clock enable bit 0 = Disable UART clock 1 = Enable UART clock W90N740CD/W90N740CDG - 34 - ...
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... External I/O Control with 8/16/32 bit external data bus Cost-effective memory-to-peripheral DMA interface SDRAM Controller supports external SDRAM & the maximum size of each device is 32MB ROM/FLASH & External I/O interface Support for PCMCIA 16-bit PC Card devices W90N740CD/W90N740CDG PLL OUTPUT CLOCK 0 58.594 KHz ...
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... The HADDR prefixes have been omitted on the following tables. A14 ~ A0 are the Address pins of the W90N740 EBI interface; A14 and A13 are the Bank Selected Signal of SDRAM. W90N740CD/W90N740CDG - 36 - ...
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... Total Type R/C (BS1) ** 16M 2Mx8 11x9 16M 1Mx16 11x8 64M 8Mx8 12x9 64M 4Mx16 12x8 64M 2Mx32 11x8 128M* 16Mx8 12x10 128M 8Mx16 12x9 128M 4Mx32 12x8 256M* 32Mx8 13x10 256M* 16Mx16 13x9 W90N740CD/W90N740CDG A13 A12 A11 A10 A9 A8 (BS0 ...
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... Total Type R/C (BS1) ** 16M 2Mx8 11x9 16M 1Mx16 11x8 64M 8Mx8 12x9 64M 4Mx16 12x8 64M 2Mx32 11x8 128M 16Mx8 12x10 128M 8Mx16 12x9 128M 4Mx32 12x8 256M* 32Mx8 13x10 256M 16Mx16 13x9 W90N740CD/W90N740CDG A13 A12 A11 A10 A9 A8 (BS0 ...
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... Total Type R/C (BS1) ** 16M 2Mx8 11x9 16M 1Mx16 11x8 64M 8Mx8 12x9 64M 4Mx16 12x8 64M 2Mx32 11x8 128M 16Mx8 12x10 128M 8Mx16 12x9 128M 4Mx32 12x8 256M 32Mx8 13x10 256M 16Mx16 13x9 W90N740CD/W90N740CDG A13 A12 A11 A10 A9 A8 (BS0 ...
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... MRSET bit enable to execute the Mode Register Set command. 7.3.2.3. SDRAM Interface A[24:0] D[31:0] MCLK MCKE nSCS[1:0] nSRAS nSCAS nSWE nSDQM[3:0] W90N740 W90N740CD/W90N740CDG A[10:0] A[10:0] A13 BS0 A14 BS1 CLK CKE nSCS0 nCS nRAS nCAS ...
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... ADDRESS EBICON 0xFFF0.1000 RESERVED REFRAT W90N740CD/W90N740CDG R/W DESCRIPTION R/W EBI control register R/W ROM/FLASH control register R/W SDRAM bank 0 configuration register R/W SDRAM bank 1 configuration register R/W SDRAM bank 0 timing control register R/W SDRAM bank 1 timing control register R/W External I/O 0 control register ...
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... If pin D14 is pull-down, the external memory format is Big Endian mode. If pin D14 is pull-up, the external memory format is Little Endian mode. For more detail, refer to Power-On Setting of System Manager. ROM/Flash Control Register （ROMCON） REGISTER ADDRESS ROMCON 0xFFF0.1004 W90N740CD/W90N740CDG value period = fMCLK ...
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... The start address is calculated as ROM/Flash bank base pointer << 18. The base address pointer together with the “SIZE” bits constitutes the whole address range of each bank. SIZE [18:16] ：The size of ROM/FLASH memory SIZE [10: tPA [11:8]：Page mode access cycle time tPA [11: W90N740CD/W90N740CDG 28 27 BASADDR BTSIZE MCLK ...
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... BTSIZE [3:2] ：Read only, the boot ROM/FLASH data bus width This ROM/Flash bank is designed for a boot ROM. BASADDR bits determine its start address. The external data bus width is determined by the data bus signals D [13:12] power-on setting. BTSIZE [3:2] BUS WIDTH RESERVED PGMODE [1:0] ：Page mode configuration PGMODE [1: W90N740CD/W90N740CDG MCLK ...
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... There are two configuration registers SDCONF0、SDCONF1 for SDRAM bank 0、bank 1 respectively. Each bank can have a different configuration. REGISTER ADDRESS SDCONF0 0xFFF0.1008 SDCONF1 0xFFF0.100C W90N740CD/W90N740CDG Fig7.3.2 ROM/FLASH Read Operation Timing R/W DESCRIPTION R/W SDRAM bank 0 configuration register R/W SDRAM bank 1 configuration register - 45 - RESET VALUE 0x0000 ...
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... COMPBK [7] ： Number of component bank in SDRAM bank 0/1 Indicates the number of component bank ( banks) in external SDRAM bank 0/ banks banks DBWD [6:5] ：Data bus width for SDRAM bank 0/1 Indicates the external data bus width connect with SDRAM bank 0/1 W90N740CD/W90N740CDG BASADDR 21 ...
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... Timing Control Registers （SDTIME0/1） W90N740 offers the flexible timing control registers to control the generation and processing of the control signals and can achieve you use different speed of SDRAM REGISTER ADDRESS SDTIME0 0xFFF0.1010 0xFFF0.1014 SDTIME1 W90N740CD/W90N740CDG Size of SDRAM （Byte） R/W ...
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... RESERVED 7 6 tRDL tRCD [10:8] ：SDRAM bank 0/1, /RAS to /CAS delay (see Fig 7.3.4) tRCD [10: tRDL [7:6] ：SDRAM bank 0/1, Last data in to pre-charge command (see Fig 7.3.5) tRDL [7: W90N740CD/W90N740CDG RESERVED RESERVED tRP tRCD tRAS MCLK MCLK ...
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... Row pre-charge time (see Fig 7.3.4) tRP [5: W90N740CD/W90N740CDG Fig 7.3.4 Access timing 1 of SDRAM Publication Release Date: Aug. 18, 2005 - 49 - MCLK Revision A6 ...
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... Row active time (see Fig 7.3.4) tRAS [2: W90N740CD/W90N740CDG Fig 7.3.5 Access timing 2 of SDRAM - 50 - MCLK ...
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... I/O bank. SIZE [18:16] ：The size of the external I/O bank 0~3 SIZE [18:16 W90N740CD/W90N740CDG R/W DESCRIPTION R/W External I/O 0 control register R/W External I/O 1 control register R/W External I/O 2 control register R/W External I/O 3 control register 28 27 BASADDR tACC tCOS ...
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... When ADRS is set, EBI bus is alignment to byte address format, and ignores DBWD [1:0] setting. tACC [14:11] ：Access cycles （nOE or nWE active time）for external I/O bank 0~3 tACC [14:11 tCOH [10:8] ：Chip selection hold-on time on nWBE for external I/O bank 0~3 tCOH [10: W90N740CD/W90N740CDG MCLK 0 Reserved tACC [14:11] MCLK ...
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... I/O bank 0~3 When ROM/Flash memory bank is configured, the access to its bank stretches chip selection time before the nOE or new signal is activated. tCOS [4: DBWD [1:0] ：Programmable data bus width for external I/O bank 0~3 DBWD [1: W90N740CD/W90N740CDG WIDTH OF DATA BUS MCLK 0 1 ...
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... DLH_CLK_REF [31:16]: Latch DLH_CLK clock tree by HCLK positive edge. (Read Only) SWPON [8]: SDRAM Initialization by Software trigger Set this bit will issue a SDRAM power on default setting command, this bit will be auto-clear by hardware. W90N740CD/W90N740CDG Fig 7.3.6 External I/O write operation timing R/W DESCRIPTION ...
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... Note: P-x means MCLKO shift “X” gates delay by refer HCLK positive edge, N-x means MCLKO shift “X” gates delay by refer HCLK negative edge. MCLK is the output pin of MCLKO, which is a internal signal on chip. W90N740CD/W90N740CDG GATE DLH_CLK_SKEW [7:4] DELAY P-0 ...
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... A cache line is then selected to receive the data that will be coming from the bus. A least recently used (LRU) replacement algorithm is used to select a line when no empty lines are available. W90N740CD/W90N740CDG ON-CHIP RAM Size ...
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... Cache to guarantee quick access. Lockdown can be performed with a granularity of one cache line. The smallest space, which can be locked down words. After a line is locked, it operates as a regular instruction SRAM. Lines locked are not replaced during misses and not affected by flush per line command. W90N740CD/W90N740CDG Publication Release Date: Aug. 18, 2005 - 57 - Revision A6 ...
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... The unlock all operation is used to unlock the whole I-Cache. This operation is performed on all cache lines. In case a line is locked unlocked and starts to operate as regular valid cache line. In case a line is not locked invalid, no operation is performed. To unlock the whole cache, set the ULKA and ICAH bits. W90N740CD/W90N740CDG - 58 - ...
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... This reduces the effective write memory cycle time from the time required for a main memory cycle to the cycle time of the high-speed cache. Write Miss：Data is only written into write buffer, not to the cache (write no allocate). W90N740CD/W90N740CDG Publication Release Date: Aug. 18, 2005 - 59 - ...
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... The unlock all operation is used to unlock the whole D-Cache. This operation is performed on all cache lines. In case a line is locked unlocked and starts to operate as regular valid cache line. In case a line is not locked invalid, no operation is performed. To unlock the whole cache, set the ULKA and DCAH bits. W90N740CD/W90N740CDG - 60 - ...
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... RESERVED WRBEN [2] ：Write buffer enable When set to “1”, write buffer operation is enabled. Write buffer is disabled after reset. W90N740CD/W90N740CDG R/W Description R/W Cache configuration register R/W Cache control register R/W Cache address register R/W Cache test register 0 R Cache test register 1 ...
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... ULKS [6] ：Unlock I-Cache/D-Cache single line Unlocks the I-Cache/D-Cache per line. Both WAY and ADDR bits in CAHADR register must be specified. ULKA [5] ：Unlock I-Cache/D-Cache entirely Unlocks the entire I-Cache/D-Cache, the lock bit “L” will be cleared to 0. W90N740CD/W90N740CDG R/W DESCRIPTION R/W Cache control register 29 ...
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... Cache Address Register (CAHADR) W90N740 Cache Controller supports one address register. This address register is used with the command set in the control register (CAHCON) by specifying instruction/data address. REGISTER ADDRESS CAHADR 0xFFF0.2008 31 30 WAY W90N740CD/W90N740CDG R/W DESCRIPTION R/W Cache address register ADDR ADDR ADDR ...
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... All the registers are described below. 7.5.1.1. Rx Buffer Descriptor (RXBD Status O O: Ownership bits BIT [31: 30 CPU = DMA W90N740CD/W90N740CDG Data Buffer Starting Address NAT Information (Reserved) Next Descriptor Starting Address - Frame Length ...
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... The value current packet IP/port is hit in the IP address location. PortHit: current packet is hit on Port Number The value current packet IP/port is hit in the port number location. Inverse: current hit entry is setting on inverse mode The value current hit entry is on inverse mode. W90N740CD/W90N740CDG IPHit ...
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... TCP information: URG (bit 29), ACK, PSH, RST, SYN, FIN (bit 24) The six bit values show current TCP status, and are transparent to the six bits in TCP header. The values are valid if current packet is TCP type and Hit is set. UCK_Err: TCP/UCKS Error TU_Err: TCP/UDP Error NH_Err: No Hit Error W90N740CD/W90N740CDG TCP information 21 ...
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... The L/W value the hit port is internal port, and 0 if the hit port is external port. The value is valid if Hit is set. Hit: current packet is hit with NAT entry table The value current packet IP/port is in the entry list. If NAT is disabled, the bit is reserved. W90N740CD/W90N740CDG Publication Release Date: Aug. 18, 2005 - 67 - Revision A6 ...
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... Tx Status: Transmit Status This field is updated by the EMC after transmission. 7.5.1.9. Frame Length This field is the size of the transmit frame. Next Descriptor Starting Address This field is the starting address of the next frame descriptor. W90N740CD/W90N740CDG Data Buffer Starting Address Next Descriptor Starting Address ...
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... Transmit is paused by a remote flow control command. SQE: SQE error After transmitting a frame, set if the fake collision signal did not come from the PHY for 1.6 µs. CCNT: Transmit Collision Count Count of collisions during transmission of a single packet. After 16 collisions, CCNT is 1111, and TXABT is set. W90N740CD/W90N740CDG SEQ 20 ...
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... CAM6L_0 0xFFF0.303C CAM7M_0 0xFFF0.3040 CAM7L_0 0xFFF0.3044 CAM8M_0 0xFFF0.3048 CAM8L_0 0xFFF0.304C CAM9M_0 0xFFF0.3050 W90N740CD/W90N740CDG R/W DESCRIPTION R/W CAM Command Register R/W CAM enable register R/W CAM0 Most Significant Word Register R/W CAM0 Least Significant Word Register R/W CAM1 Most Significant Word Register ...
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... TXDLSA_0 0xFFF0.309C RXDLSA_0 0xFFF0.30A0 DMARFC_0 0xFFF0.30A4 TSDR_0 0xFFF0.30A8 RSDR_0 0xFFF0.30AC FIFOTHD_0 0xFFF0.30B0 W90N740CD/W90N740CDG R/W DESCRIPTION R/W CAM9 Least Significant Word Register R/W CAM10 Most Significant Word Register R/W CAM10 Least Significant Word Register R/W CAM11 Most Significant Word Register R/W CAM11 Least Significant Word Register ...
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... R/W CAM2 Least Significant Word Register CAM3M_1 0xFFF0.3820 CAM3L_1 0xFFF0.3824 CAM4M_1 0xFFF0.3828 CAM4L_1 0xFFF0.382C R/W CAM4 Least Significant Word Register W90N740CD/W90N740CDG R/W DESCRIPTION R MAC Receive Pause count register R MAC Receive Pause Current Count Register R MAC Remote pause count register Current Transmit Descriptor Start Address ...
Page 76
... R/W MAC Command Register MIID_1 0xFFF0.3890 MIIDA_1 0xFFF0.3894 MPCNT_1 0xFFF0.3898 W90N740CD/W90N740CDG R/W DESCRIPTION R/W CAM5 Most Significant Word Register R/W CAM5 Least Significant Word Register R/W CAM6 Most Significant Word Register R/W CAM7 Most Significant Word Register R/W CAM7 Least Significant Word Register ...
Page 77
... MAC in promiscuous mode, use CAMCMR_x settings to accept packets with all three types of destination address. The three types of destination address packets are as follows: 1. Station packets, xxxxxxx0-xxxxxxxx-xxxxxxxx-xxxxxxxx-xxxxxxxx-xxxxxxxx 2. Multicast packet, xxxxxxx1-xxxxxxxx-xxxxxxxx-xxxxxxxx-xxxxxxxx-xxxxxxxx. (but x not all 1) 3. Broadcast packet, 11111111-11111111-11111111-11111111-11111111-11111111 W90N740CD/W90N740CDG R/W DESCRIPTION Transmit Descriptor Link List Start Address register ...
Page 78
... Set this bit to accept any packet with a broadcast address. AMP [1]: Accept Multicast Packet Default value: 0 Set this bit to accept any packet with a multicast address. AUP [0]: Accept Unicast Packet Default value: 0 Set this bit to accept any packet with a unicast address. W90N740CD/W90N740CDG DESCRIPTION 28 27 Reserved 20 19 ...
Page 79
... SDPZ bit in the MCMDR (MAC Command Register). The CPU uses the CAM address register as a database for destination address. To activate the CAM function, the appropriate enable bit has to be set in the CAMEN register. W90N740CD/W90N740CDG DESCRIPTION CAM enable register CAM enable register ...
Page 80
... CAMxL} : destination address (6 byte), with 2 bytes in CAMxL and 4 bytes in CAMxM, (CAM15M and CAM15L excluded). For example, if the address of Entry CAM 1 is desired to store 12-34-56-78-90-13, then the content of CAM1M is 12-34-56-78, and the content of CAM1L is 90-13-00-00. W90N740CD/W90N740CDG R/W DESCRIPTION CAM0 Most Significant Word Register ...
Page 81
... R/W MIEN_1 R/W 0xFFF0.3088 MIEN_2 R/W 0xFFF0.3888 EnTDU EnLC EnTXABT Reserved EnCFR EnNATErr 7 6 EnMMP EnRP EnALIE W90N740CD/W90N740CDG Length / Type (2 bytes Op-code (2 bytes) (Most Significant Byte Op-code (2 bytes Operand (2 bytes) (Most Significant Byte Operand (2 bytes Reserved Reserved DESCRIPTION MAC Interrupt Enable Register ...
Page 82
... Set this bit to enable the interrupt, which is generated when the MAC transmits, or discards one packet. EnTXEMP [17]: Enable Transmit FIFO Empty interrupt Default value: 0 Set this bit to enable the interrupt, which is generated when MAC transmit FIFO becomes empty (underflow) during a packet transmission. W90N740CD/W90N740CDG Publication Release Date: Aug. 18, 2005 - 79 - Revision A6 ...
Page 83
... Set this bit to enable the interrupt, when the length field of the current frame is received. EnDFO [8]: Enable DMA receive frame over maximum size interrupt Default value: 0 Set this bit to enable the interrupt, when the received frame size is larger than the value stored in RXMS. W90N740CD/W90N740CDG - 80 - ...
Page 84
... PHY asserted Rx_er during packet reception. EnRXINTR [0]: Enable Interrupt on Receive interrupt Default value: 0 Set this bit to enable the interrupt, which is generated if the reception of a packet caused an interrupt to be generated. This includes a good received interrupt, if the EnRXGD bit is set. W90N740CD/W90N740CDG Publication Release Date: Aug. 18, 2005 - 81 - Revision A6 ...
Page 85
... EMC LAN port and EMC WAN port) to let the NAT accelerator work properly. LPCS [23]: Low Pin Count Package Switch Always set: 0 EnRMII [22]: Enable RMII Default value: 0 Set this bit to select RMII interface. W90N740CD/W90N740CDG R/W DESCRIPTION R/W MAC Command Register R/W MAC Command Register ...
Page 86
... TXON [8]: Transmit On Default value: 0 When this bit is set, the transmission process will be started. If the bit is clear, transmissions will stop after the current packet is transmitted completely. Users should change the bit when the MAC is in idle state. W90N740CD/W90N740CDG MAC 1 MAC 0 INTERFACE INTERFACE ...
Page 87
... W90N740 provides MII management function to let user access the registers of the external physical layer device. Setting options in MII management registers does not affect the MAC controller operation. REGISTER ADDRESS MIID_0 0xFFF0.3090 MIID_1 0xFFF0.3890 W90N740CD/W90N740CDG R/W DESCRIPTION R/W MII Management Data Register R/W MII Management Data Register Reserved Reserved 13 12 ...
Page 88
... MDCCR [23:20]: MDC clock rating Default value: 0x009 The 4-bit value is to set the MDC clock period. MDCCR [23:20 Default MDCCR [23:20 W90N740CD/W90N740CDG DESCRIPTION 28 27 Reserved 20 19 MDCON RESET VALUE PreSP BUSY PHYAD PHYRAD MDC clock period 4 x (1/Fmclk (1/Fmclk (1/Fmclk) ...
Page 89
... MII management function are illustrated as the figure below. Each bit in the management data frame (MDIO) are synchronized at the rising edge of the MII management clock (MDC). MII Management Protocol ACCESS PREAMBLE START OPERATION READ 1… 1… WRITE W90N740CD/W90N740CDG MII MANAGEMENT PROTOCOL PHYADDR PHYREGADDR 10 AAAAA RRRRR 01 AAAAA RRRRR - 86 - ...
Page 90
... FIFO overflows, or because the RxON bit is cleared. This count does not include the number of packets rejected by the CAM. CRC error count (CECnt): The number of packets received with a CRC error. The counter will be increment at the end of packet reception if the MISTA indicates the CRC errors. W90N740CD/W90N740CDG R/W DESCRIPTION R/W ...
Page 91
... The system would ignore the least 2 significant bits to fit word alignment. DMA Receive Descriptor Link List Start Address Register (RXDLSA_0, RXDLSA_1) REGISTER ADDRESS RXDLSA_0 0xFFF0.30A0 RXDLSA_1 0xFFF0.38A0 W90N740CD/W90N740CDG R/W DESCRIPTION Transmit Descriptor Link-list Start Address R/W register Transmit Descriptor Link-list Start Address R/W register TXDLSA TXDLSA ...
Page 92
... Default value: 0800h This value controls the maximum bytes for a received frame can be saved to memory. If the received frame size exceeds the value stored in this location and the EnDFO is set, an error interrupt is reported. The default maximum size is 2K bytes. W90N740CD/W90N740CDG R/W DESCRIPTION R/W ...
Page 93
... While the receive descriptor is unavailable, the Rx state machine will enter Halt state. The user has to issue a write command with any data to Receive Start Demand register to restart the Rx operation. Only while Rx state machine stay at Halt state, the write command to Receive Start Demand register can affect the Rx operation. W90N740CD/W90N740CDG R/W DESCRIPTION W ...
Page 94
... This value controls the transmit FIFO low threshold. If transmitting packet number is less than the setting value, Tx DMA will request the arbiter to get data from memory. W90N740CD/W90N740CDG R/W DESCRIPTION R/W ...
Page 95
... This field will be set if access error from EMC to memory (for example, address undefined in system) is occurred. If the status and EnTxBErr in MIEN are both set, the EMC_TxINT will be triggered. If the status is set, the Tx operation will be ceased and the software reset to reset the EMC is recommended. W90N740CD/W90N740CDG DESCRIPTION MAC Interrupt Status Register ...
Page 96
... Set when MAC transmitting FIFO becomes empty (underflow) during a packet transmission. TXINTR [16]: Interrupt on Transmit Default value: 0 This bit is set if transmission of a packet caused an interrupt condition. CFR [14]: Control Frame Receive Default value: 0 This field will be set if the incoming frame is a MAC control frame (type==8808h). W90N740CD/W90N740CDG Publication Release Date: Aug. 18, 2005 - 93 - Revision A6 ...
Page 97
... MMP [7]: More Missed Packets than miss rolling over counter flag Default value: 0 This bit is automatically set when the missed error counter rolls over. RP [6]: Runt Packet Default value: 0 This bits is set, it indicates that the received packet length is less than 64 bytes (unless ARP in MCMDR is set). W90N740CD/W90N740CDG - 94 - ...
Page 98
... EnRXGD bit in MIEN is set. MAC General Status Register (MGSTA_0, MGSTA_1) REGISTER ADDRESS MGSTA_0 0xFFF0.30B8 MGSTA_1 0xFFF0.38B8 Reserved 7 6 CCNT W90N740CD/W90N740CDG R/W DESCRIPTION R/W MAC General Status Register R/W MAC General Status Register 28 27 Reserved 20 19 Reserved 12 11 TXHA Reserved - 95 - RESET VALUE 0x0000 ...
Page 99
... MAC Received Pause Count Register (MRPC_0, MRPC_1) The received pause count register, MRPC, stores the value of the 16-bit received pause counter read only. REGISTER ADDRESS R/W MRPC_0 0xFFF0.30BC MRPC_1 0xFFF0.38BC W90N740CD/W90N740CDG DESCRIPTION R MAC Receive Pause count register R MAC Receive Pause count register - 96 - RESET VALUE 0x0000.0000 0x0000.0000 ...
Page 100
... MRPC [15:0]: MAC Received Pause Count Register Default value: 0 The count value indicates the number of time slots the transmitter was paused due to the receipt of control pause operation packets from the MAC. W90N740CD/W90N740CDG 28 27 Reserved 20 19 Reserved 12 11 MRPC MRPC R/W DESCRIPTION ...
Page 101
... The count value indicates the number of time slots that a remote MAC was paused as a result of its sending control pause operation packets. DMA Receive Frame Status Register (DMARFS_0, DMARFS_1) REGISTER ADDRESS DMARFS_0 0xFFF0.30C8 DMARFS_1 0xFFF0.38C8 W90N740CD/W90N740CDG R/W DESCRIPTION R MAC Remote pause count register R MAC Remote pause count register 28 27 Reserved 20 19 Reserved 12 11 MREPC MREPC ...
Page 102
... CTXDSA [31:0]: Current Transmit Descriptor Start Address Default value: 0000h This register reports the start address of the current transmit descriptor used by EMC. W90N740CD/W90N740CDG R/W DESCRIPTION Current Transmit Descriptor Start Address R Register Current Transmit Descriptor Start Address R Register 28 27 CTXDSA 20 19 CTXDSA ...
Page 103
... CRXDSA_1 0xFFF0.38D4 CRXDSA [31:0]: Current Receive Descriptor Start Address Default value: 0000h This register reports the start address of the current receive descriptor used by EMC. W90N740CD/W90N740CDG DESCRIPTION R Current Transmit Buffer Start Address Register R Current Transmit Buffer Start Address Register CTXBSA CTXBSA ...
Page 104
... Hardware acceleration on IP address / port number look up and replacement for network address • Translation, including MAC address translation • Provide 64 entries of translation table • Support TCP / UDP packets W90N740CD/W90N740CDG Description Current Receive Buffer Start Address Register Current Receive Buffer Start Address Register ...
Page 105
... The port number in the TCP/UDP header is replaced with new port number 3. Recalculate the IP checksum 4. Recalculate the TCP/UDP checksum NATA do MAC address replacement process : Replace MAC 0 and MAC 1 address in the MAC header W90N740CD/W90N740CDG NAT hit? Yes Rx triggers NAT processing NATA exit NAT process ...
Page 106
... NATCFG63 0xFFF0.61FC EXMACM 0xFFF0.6200 EXMACL 0xFFF0.6204 INMACM 0xFFF0.6208 INMACL 0xFFF0.620C W90N740CD/W90N740CDG R/W DESCRIPTION R/W NAT Command Register W NAT Counter 0 Clear Register W NAT Counter 1 Clear Register W NAT Counter 2 Clear Register W NAT Counter 3 Clear Register R/W NAT Entry 0 Configuration Register R/W NAT Entry 1 Configuration Register ...
Page 107
... LSPN63 0xFFF0.6FEC LSMAC63M 0xFFF0.6FF0 LSMAC63L 0xFFF0.6FF4 RSMAC63M 0xFFF0.6FF8 RSMAC63L 0xFFF0.6FFC W90N740CD/W90N740CDG R/W DESCRIPTION R/W NAT Masquerading IP Address Entry 0 R/W NAT Masquerading Port Number Entry 0 R/W Local Station IP Address Entry 0 R/W Local Station Port Number Entry 0 Local Station MAC Address Most Significant Word ...
Page 108
... Set this bit to start NAT function. The EMC Rx will begin packet parsing and lookup procedure if this bit is set. Clear this bit will stop all NAT operations. NAT Counter x Clear Register (NATCCLRx)( REGISTER ADDRESS NATCCLR0 0x7FF06010 | | NATCCLR3 0x7FF0601C W90N740CD/W90N740CDG DESCRIPTION 28 27 Reserved 20 19 Reserved 12 11 Reserved ...
Page 109
... CLREH21 15 14 CLRCNT31 CLRCNT30 CLRCNT29 7 6 CLRCNT23 CLRCNT22 CLRCNT21 7.6.2.3. NATCCLR2 31 30 CLREH47 CLREH46 CLREH45 23 22 CLREH39 CLREH38 CLREH37 15 14 CLRCNT47 CLRCNT46 CLRCNT45 7 6 CLRCNT39 CLRCNT38 CLRCNT37 W90N740CD/W90N740CDG CLREH12 CLREH11 CLREH 4 CLREH CLRCNT12 CLRCNT11 CLRCNT4 CLRCNT3 CLREH28 CLREH27 CLREH20 CLREH19 13 12 ...
Page 110
... Otherwise there may be an error condition occurred, for example, when S/W program has changed entry data, but the previous hit packet is being processed, and cannot find replacement data. REGISTER ADDRESS NATCFG0 0x7FF06100 | | NATCFG63 0x7FF061FC W90N740CD/W90N740CDG 28 27 CLREH60 CLREH59 20 19 CLREH52 CLREH51 12 11 ...
Page 111
... Set this bit to change comparison and replacement field in packets. For example, at the WAN port, destination address and port {DA, DP} is compared for inverse bit (I bit) clear bit is set, source address and port {SA, SP} is compared instead of {DA, DP applicable for IP filter. PxRE [4]: Port Number Replacement Enable at Entry x Default value: 0 W90N740CD/W90N740CDG EHCNTx ...
Page 112
... LP: local mapping port number SA: (IP) address at source field SP: port number at source field DA: (IP) address at destination field DP: port number at destination field Data Content in the NATA table Field 0 Entry Entry …. …. Entry W90N740CD/W90N740CDG Field 1 Field …. … Publication Release Date: Aug. 18, 2005 - 109 - Field … ...
Page 113
... EXMACL (INMACM, INMACL)}: MAC address (6 bytes), with 2 bytes in EXMACL {LSMACxM, LSMACxL (RSMACxM, RSMACxL)}: MAC address (6 bytes), with 2 bytes in LSMACxL For example, if the External MAC address is desired to store 12-34-56-78-90-13, then the content of EXMACM is 12-34-56-78, and the content of EXMACL is 90-13-00-00. W90N740CD/W90N740CDG REPLACEMENT DA with LA (if AxRE set) ...
Page 114
... On the other hand, when the external MAC receive packet, its destination address and destination port number is compared. If the result is hit, then its destination address and destination port number are be replaced by LSADx and LSPNx, and the packet is transmitted to local MAC. W90N740CD/W90N740CDG 28 27 ...
Page 115
... MASADx, LSADx MASPNx, LSPNx For example, if the masquerading address is 140.112.2.100 and the masquerading port number is 7500, then the value in MASAD is 8C-70-02-64, and the value in MASPN is 00-00-1D-4C. W90N740CD/W90N740CDG Address Byte 4 (Most Significant Byte Address Byte Address Byte Address Byte Reserved 21 20 ...
Page 116
... The assertion of a single GDMA request causes all of the data to be transferred in a single operation. The GDMA transfer is completed when the current transfer count register reaches zero. • Demand Mode The GDMA continues transferring data until the GDMA request input nXDREQ1/2/3 becomes inactive. W90N740CD/W90N740CDG Publication Release Date: Aug. 18, 2005 - 113 - Revision A6 ...
Page 117
... RESERVED SABNDERR DABNDERR RESERVED 7 6 SAFIX DAFIX W90N740CD/W90N740CDG R/W DESCRIPTION Channel 0 Control Register Channel 0 Source Base Address Register Channel 0 Destination Base Address Register Channel 0 Transfer Count Register R Channel 0 Current Source Address Register Channel 0 Current Destination Address R Register R Channel 0 Current Transfer Count Register ...
Page 118
... Software can request the GDMA transfer service by setting this bit to 1. This bit is automatically cleared by hardware when the transfer is completed. This bit is available only while GDMAMS [3:2] register bits are set on software mode (memory to memory). W90N740CD/W90N740CDG Publication Release Date: Aug. 18, 2005 - 115 - ...
Page 119
... GDMA operation is stopped SAFIX [7]: Source Address Fixed 0 = Source address is changed during the GDMA operation not change the destination address during the GDMA operation. This feature can be used when data were transferred from a single source to multiple destinations. W90N740CD/W90N740CDG - 116 - ...
Page 120
... The GDMA channel starts reading its data from the source address as defined in this source base address register. REGISTER ADDRESS R/W GDMA_SRCB0 0xFFF0.4004 R/W Channel 0 Source Base Address Register GDMA_SRCB1 0xFFF0.4024 R/W Channel 1 Source Base Address Register W90N740CD/W90N740CDG DESCRIPTION 28 27 SRC_BASE_ADDR [31:24 SRC_BASE_ADDR [23:16 SRC_BASE_ADDR [15: SRC_BASE_ADDR [7:0] - 117 - RESET VALUE 0x0000.0000 0x0000 ...
Page 121
... Channel 0/1 Transfer Count Register (GDMA_TCNT0, GDMA_TCNT1) REGISTER ADDRESS GDMA_TCNT0 0xFFF0.400C GDMA_TCNT1 0xFFF0.402C TFR_CNT [23:0]: 24-bit Transfer Count The TFR_CNT represents the required number of GDMA transfers. The maximum transfer count is 16M –1. W90N740CD/W90N740CDG R/W DESCRIPTION DST_BASE_ADDR [31:24 DST_BASE_ADDR [23:16 DST_BASE_ADDR [15:8] 5 ...
Page 122
... During a block transfer, the GDMA determines the successive destination addresses by adding to or subtracting from the destination base address. Depending on the settings you make to the control register, the current destination address will remain the same or will be incremented or decremented. W90N740CD/W90N740CDG R/W DESCRIPTION R ...
Page 123
... Channel 0/1 Current Transfer Count Register (GDMA_CTCNT0, GDMA_CTCNT1) The Current transfer count register indicates the number of transfer being performed. REGISTER ADDRESS GDMA_CTCNT0 0xFFF0.4018 GDMA_CTCNT1 0xFFF0.4038 CURRENT_TFR_CNT [23:0]: Current Transfer Count W90N740CD/W90N740CDG R/W DESCRIPTION R Channel 0 Current Transfer Count Register R Channel 1 Current Transfer Count Register Reserved CURENT_TFR_CNT [23:16 ...
Page 124
... Open Host Controller Interface (OHCI) 1.1 compatible. • Supports both low-speed (1.5 Mbps) and full-speed (12Mbps) USB devices. • Built-in DMA for real-time data transfer • Option for on-chip USB transceiver or external USB transceiver W90N740CD/W90N740CDG Publication Release Date: Aug. 18, 2005 - 121 - Revision A6 ...
Page 125
... HcRhDescriptorB 0xFFF0.504C HcRhStatus 0xFFF0.5050 HcRhPortStatus [1] 0xFFF0.5054 HcRhPortStatus [2] 0xFFF0.5058 W90N740CD/W90N740CDG R/W DESCRIPTION R Host Controller Revision Register R/W Host Controller Control Register R/W Host Controller Command Status Register R/W Host Controller Interrupt Status Register R/W Host Controller Interrupt Enable Register R/W Host Controller Interrupt Disable Register ...
Page 126
... R/W W90N740CD/W90N740CDG R/W DESCRIPTION R Host Controller Revision Register DESCRIPTION Revision Indicates the Open HCI Specification revision number implemented by the Hardware. Host Controller supports 1.1 specification. (X.Y = XYh) Reserved. Read/Write 0's R/W DESCRIPTION R/W Host Controller Control Register DESCRIPTION ...
Page 127
... Continued. Register: HcControl BITS RESET R/W 7-6 00b R R R/W 31- W90N740CD/W90N740CDG DESCRIPTION HostControllerFunctionalState This field sets the Host Controller state. The Controller may force a state change from USPEND signaling from a downstream port. States are: 00 ESET 01 ESUME 10 PERATIONAL 11 USPEND InterruptRouting This bit is used for interrupt routing: 0: Interrupts routed to normal interrupt mechanism (INT) ...
Page 128
... R/W 15 17-16 00b 31- W90N740CD/W90N740CDG R/W DESCRIPTION Host Controller Command Status R/W Register DESCRIPTION HostControllerReset This bit is set to initiate the software reset. This bit is cleared by the Host Controller, upon completed of the reset operation. ControlListFilled Set to indicate there is an active ED on the Control List. It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List ...
Page 129
... R W90N740CD/W90N740CDG R/W DESCRIPTION R/W Host Controller Interrupt Status Register DESCRIPTION SchedulingOverrun Set when the List Processor determines a Schedule Overrun has occurred. WritebackDoneHead Set after the Host Controller has written HcDoneHead to HccaDoneHead. StartOfFrame Set when the Frame Management block signals a ‘Start of Frame’ ...
Page 130
... R R R/W W90N740CD/W90N740CDG R/W DESCRIPTION R/W Host Controller Interrupt Enable Register DESCRIPTION SchedulingOverrunEnable 0: Ignore 1: Enable interrupt generation due to Scheduling Overrun. WritebackDoneHeadEnable 0: Ignore 1: Enable interrupt generation due to Write-back Done Head. StartOfFrameEnable 0: Ignore 1: Enable interrupt generation due to Start of Frame. ResumeDetectedEnable 0: Ignore 1: Enable interrupt generation due to Resume Detected ...
Page 131
... R R R/W W90N740CD/W90N740CDG R/W DESCRIPTION R/W Host Controller Interrupt Disable Register DESCRIPTION SchedulingOverrunEnable 0: Ignore 1: Disable interrupt generation due to Scheduling Overrun. WritebackDoneHeadEnable 0: Ignore 1: Disable interrupt generation due to Write-back Done Head. StartOfFrameEnable 0: Ignore 1: Disable interrupt generation due to Start of Frame. ResumeDetectedEnable 0: Ignore 1: Disable interrupt generation due to Resume Detected ...
Page 132
... ADDRESS HcControlHeadED 0xFFF0.5020 Register: HcControlHeadED BITS RESET R/W 3 31-4 0h R/W W90N740CD/W90N740CDG R/W DESCRIPTION R/W Host Controller Communication Area Register 0x0000.0000 DESCRIPTION R/W DESCRIPTION R/W Host Controller Period Current ED Register DESCRIPTION Reserved. Read/Write 0's PeriodCurrentED Pointer to the current Periodic List ED. R/W DESCRIPTION ...
Page 133
... REGISTER ADDRESS HcBulkCurrentED 0xFFF0.502C Register: HcBulkCurrentED BITS RESET R/W 3 31-4 0h R/W W90N740CD/W90N740CDG R/W DESCRIPTION Host Controller Control Current ED R/W Register DESCRIPTION Reserved. Read/Write 0's ControlCurrentED Pointer to the current Control List ED. R/W DESCRIPTION R/W Host Controller Bulk Head ED Register 0x0000.0000 DESCRIPTION R/W ...
Page 134
... Register: HcFmInterval BITS RESET R/W 13-0 2EDFh R/W 15- 30-16 31 W90N740CD/W90N740CDG R/W DESCRIPTION R/W Host Controller Done Head Register DESCRIPTION Reserved. Read/Write 0's DoneHead Pointer to the current Done List Head ED. R/W DESCRIPTION R/W Host Controller Frame Interval Register DESCRIPTION FrameInterval This field specifies the length of a frame as (bit times - 1). For 12,000 bit times in a frame, a value of 11,999 is stored here ...
Page 135
... Register: HcFmNumber BITS RESET R/W 15 31- W90N740CD/W90N740CDG R/W DESCRIPTION R Host Controller Frame Remaining Register DESCRIPTION FrameRemaining When the Host Controller is in the U decrements each 12 MHz clock period. When the count reaches 0, (end of frame) the counter reloads with FrameInterval. loads when the Host Controller transitions into U Reserved ...
Page 136
... Register: HcLSThreshold BITS RESET R/W 11-0 628h R/W 31- W90N740CD/W90N740CDG R/W DESCRIPTION R/W Host Controller Periodic Start Register 0x0000.0000 DESCRIPTION PeriodicStart This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin. Reserved. Read/Write 0's R/W ...
Page 137
... R R/W 23- 31-24 01h R/W W90N740CD/W90N740CDG R/W DESCRIPTION Host Controller Root Hub Descriptor A R/W Register DESCRIPTION NumberDownstreamPorts table of none-4 supports two downstream ports. PowerSwitchingMode Global power switching mode implemented in HYDRA-2. This bit is only valid when NoPowerSwitching is cleared. This bit should be written '0'. ...
Page 138
... Address HcRhDescriptorB 0xFFF0.504C Register: HcRhDescriptorB Bits Reset R/W 15-0 0000h R/W 31-16 0000h R/W W90N740CD/W90N740CDG R/W Description Host Controller Root Hub Descriptor B R/W Register Description DeviceRemoveable table of none-4 ports default to removable devices Device not removable 1 = Device removable Port Bit relationship 0 : Reserved ...
Page 139
... R R R/W 30- W90N740CD/W90N740CDG R state. SB ESET R/W Description R/W Host Controller Root Hub Status Register Description (Read) LocalPowerStatus Not Supported. Always read '0'. (Write) ClearGlobalPower Writing a '1' issues a ClearGlobalPower command to the ports. Writing a '0' has no effect. OverCurrentIndicator This bit reflects the state of the OVRCUR pin. This field is only valid if NoOverCurrentProtection and OverCurrentProtectionMode are cleared ...
Page 140
... R/W W90N740CD/W90N740CDG R state. SB ESET R/W Description R/W Host Controller Root Hub Port Status [1] R/W Host Controller Root Hub Port Status [2] Description (Read) CurrentConnectStatus device connected Device connected. NOTE: If DeviceRemoveable is set (not removable) this bit is always '1'. (Write) ClearPortEnable Writing '1' a clears PortEnableStatus. Writing a '0' has no effect. ...
Page 141
... R R R/W 31- W90N740CD/W90N740CDG DESCRIPTION Reserved. Read/Write 0's (Read) PortPowerStatus This bit reflects the power state of the port regardless of the power switching mode Port power is off Port power is on. Note: If NoPowerSwitching is set, this bit is always read as '1'. (Write) SetPortPower Writing a '1' sets PortPowerStatus. Writing a '0' has no effect. ...
Page 142
... Even, odd, or no-parity bit generation and detection -- 1-, 1&1/2, or 2-stop bit generation -- Baud rate generation • Break generation and detection • False start bit detection • Parity, overrun, and framing error detection • Full prioritized interrupt system controls W90N740CD/W90N740CDG Publication Release Date: Aug. 18, 2005 - 139 - Revision A6 ...
Page 143
... REGISTER ADDRESS 0xFFF8.0000 RBR 7 6 8-bit Received Data [7:0] By reading this register, the UART will return an 8-bit data received from SIN pin (LSB first). W90N740CD/W90N740CDG R/W DESCRIPTION R Receive Buffer Register (DLAB = 0) W Transmit Holding Register (DLAB = 0) R/W Interrupt Enable Register (DLAB = 0) ...
Page 144
... MSIE [3]: MODEM Status Interrupt (Irpt_MOS) Enable 0 = Mask off Irpt_MOS 1 = Enable Irpt_MOS RLSIE [2]: Receive Line Status Interrupt (Irpt_RLS) Enable 0 = Mask off Irpt_RLS 1 = Enable Irpt_RLS THREIE [1]: Transmit Holding Register Empty Interrupt (Irpt_THRE) Enable 0 = Mask off Irpt_THRE 1 = Enable Irpt_THRE W90N740CD/W90N740CDG DESCRIPTION W Transmit Holding Register (DLAB = 8-bit Transmitted Data DESCRIPTION ...
Page 145
... Baud Rate Divisor (High Byte) [7:0] The high byte of the baud rate divider This 16-bit divider {DLM, DLL} is used to determine the baud rate as follows Baud Rate = Crystal Clock / {16 * [Divisor + 2]} Note: This definition is different from 16550 W90N740CD/W90N740CDG R/W DESCRIPTION Divisor Latch Register (LS) R/W ...
Page 146
... Transmitter Holing 0010 Third Register Empty (Irpt_THRE) MODEM Status 0000 Fourth (Irpt_MOS) Note: These definitions of bit 7, bit 6, bit 5, bit 4 are different from the 16550. W90N740CD/W90N740CDG DESCRIPTION R Interrupt Identification Register DMS INTERRUPT SOURCE None None Overrun error, parity error, framing ...
Page 147
... FME [0]: FIFO Mode Enable Because UART is always operating in the FIFO mode, writing this bit has no effect while reading always gets logical one. This bit must be 1 when other FCR bits are written to; otherwise, they will not be programmed. W90N740CD/W90N740CDG R/W DESCRIPTION W FIFO Control Register ...
Page 148
... One “ STOP bit” is generated in the transmitted data 1 = One and a half “ STOP bit” is generated in the transmitted data when 5-bit word length is selected; Two “ STOP bit” is generated when 6-, 7- and 8-bit word length is selected. W90N740CD/W90N740CDG R/W DESCRIPTION ...
Page 149
... DTR#[0]: Complement version of DTR# (Data-Terminal-Ready) signal Writing 0x00 to MCR, the DTR#, RTS#, nOUT1# and OUT2# bit are set to logic 1’s; Writing 0x0f to MCR, the DTR#, RTS#, nOUT1# and OUT2# bit are reset to logic 0’s. W90N740CD/W90N740CDG Character length DESCRIPTION Modem Control Register ...
Page 150
... This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU reads the contents of the LSR. W90N740CD/W90N740CDG Description R Line Status Register ...
Page 151
... This bit is set whenever DCD# input has changed state, and it will be reset if the CPU reads the MSR. TERI [2]: Tailing Edge of RI# This bit is set whenever RI# input has changed from high to low, and it will be reset if the CPU reads the MSR. W90N740CD/W90N740CDG R/W DESCRIPTION R ...
Page 152
... The time out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word. Once the content of time out counter (TOUT_CNT) is equal to that of time out interrupt comparator (TOIC), a receiver time out interrupt (Irpt_TOUT) is generated if TOR [7] = IER [ new incoming data word or RX FIFO empty clears Irpt_TOUT. W90N740CD/W90N740CDG R/W DESCRIPTION R/W ...
Page 153
... The reset signal will last for two clocks long and the WTRF will be set. When used as a simple timer, the interrupt and reset functions are disabled. The watchdog timer will set the WTIF each time a time-out occurs. The WTIF can be polled to check the status, and software can restart the timer by setting the WTR. W90N740CD/W90N740CDG - 150 - ...
Page 154
... CE [30]: Counter Enable 0 = Stops counting 1 = Starts counting IE [29]: Interrupt Enable 0 = Disables timer interrupt 1 = Enables timer interrupt. If timer interrupt is enabled, the timer asserts its interrupt signal when the associated counter decrements to zero. W90N740CD/W90N740CDG R/W/C DESCRIPTION R/W Timer Control Register 0 R/W Timer Control Register 1 ...
Page 155
... TICR1 TIC [23:0]: Timer Initial Count This is a 24-bit value representing the initial count. Timer will reload this value whenever the counter is decremented to zero. W90N740CD/W90N740CDG TIMER OPERATING MODE R/W/C DESCRIPTION R/W Timer Initial Control Register 0 R/W Timer Initial Control Register RESERVED ...
Page 156
... TDR [23:0]: Timer Data Register The current count is registered in this 24-bit value. Timer Interrupt Status Register (TISR) REGISTER ADDRESS R/W/C TISR 0xFFF8.1018 W90N740CD/W90N740CDG R/W/C DESCRIPTION R Timer Data Register 0 R Timer Data Register RESERVED 20 19 TDR [23:16 TDR [15: TDR [7:0] DESCRIPTION R/C ...
Page 157
... ICE debug mode acknowledge enable 0 = When DBGACK is high, the timer clock will be held matter what DBGACK is high or not, the timer clock will not be held RESERVED [8 Put the watchdog time in the normal operating mode W90N740CD/W90N740CDG R/W/C DESCRIPTION Watchdog Timer Control Register R/W ...
Page 158
... Watchdog timer reset does not occur 1 = Watchdog timer reset occurs WTRE [1]: Watchdog Timer Reset Enable Setting this bit will enable the watchdog timer reset function Disable watchdog timer reset function 1 = Enable watchdog timer reset function W90N740CD/W90N740CDG INTERRUPT TIME-OUT 21 2 clocks 22 2 ...
Page 159
... Programmable as either edge-triggered or level-sensitive for 4 external interrupt sources Programmable as either low-active or high-active for 4 external interrupt sources Priority methodology is encoded to allow for interrupt daisy-chaining Automatically mask out the lower priority interrupt during interrupt nesting Automatically clear the interrupt flag when the interrupt source is programmed to be edge- triggered W90N740CD/W90N740CDG - 156 - ...
Page 160
... USBINT1 11 Reserved 12 Reserved 13 EMCTXINT0 14 EMCTXINT1 15 EMCRXINT0 16 EMCRXINT1 17 GDMAINT0 18 GDMAINT1 W90N740CD/W90N740CDG PRIORITY MODE HIGHEST Positive Level Programmable Programmable Programmable Programmable Positive Level Positive Level Positive Level Positive Level Positive Level Reserved Reserved Positive Level Positive Level Positive Level Positive Level Positive Level ...
Page 161
... AIC_IMR 0xFFF8.2114 0xFFF8.2118 AIC_OISR AIC_MECR 0xFFF8.2120 0xFFF8.2124 AIC_MDCR AIC_SSCR 0xFFF8.2128 AIC_SCCR 0xFFF8.212C 0xFFF8.2130 AIC_EOSCR W90N740CD/W90N740CDG R/W DESCRIPTION R/W Source Control Register 1 R/W Source Control Register 2 R/W Source Control Register 3 R/W Source Control Register 4 R/W Source Control Register 5 R/W Source Control Register 6 ...
Page 162
... Interrupt sources with priority level 0 are promoted to FIQ. Interrupt sources with priority level other than 0 belong to IRQ. For interrupt sources of the same priority level, that located in the lower channel number has higher priority. W90N740CD/W90N740CDG R/W DESCRIPTION ...
Page 163
... RESERVED 15 14 IAS15 IAS14 IAS13 7 6 IAS7 IAS6 IAS5 This register indicates the status of each interrupt channel in consideration of the interrupt source type as defined in the corresponding Source Control Register, but regardless of its mask setting. W90N740CD/W90N740CDG R/W DESCRIPTION R Interrupt Raw Status Register RESERVED ...
Page 164
... ISx: Interrupt Status Indicates the status of corresponding interrupt channel 0 = Two possibilities: (1) The corresponding interrupt channel is inactive no matter whether it is enabled or disabled; ( active but not enabled 1 = Corresponding interrupt channel is both active and enabled (can assert an interrupt) W90N740CD/W90N740CDG R/W DESCRIPTION R Interrupt Status Register 29 28 ...
Page 165
... This register can help indexing into a branch table to quickly jump to the corresponding interrupt service routine. VECTOR [6:2]: Interrupt Vector interrupt occurs representing the interrupt channel that is active, enabled, and having the highest priority W90N740CD/W90N740CDG R/W DESCRIPTION R Interrupt Priority Encoding Register ...
Page 166
... This bit determines whether the corresponding interrupt channel is enabled or disabled. Every interrupt channel can be active no matter whether it is enabled or disabled interrupt channel is enabled, it does not definitely mean it is active. Every interrupt channel can be authorized by the AIC only when it is both active and enabled. W90N740CD/W90N740CDG R/W DESCRIPTION R ...
Page 167
... The AIC classifies the interrupt into FIQ and IRQ. This register indicates whether the asserted interrupt is FIQ or IRQ. If both IRQ and FIQ are equal means there is no interrupt occurred. IRQ [1]: Interrupt Request 0 = nIRQ line is inactive nIRQ line is active. FIQ [0]: Fast Interrupt Request 0 = nFIQ line is inactive nFIQ line is active W90N740CD/W90N740CDG R/W DESCRIPTION R Output Interrupt Status Register ...
Page 168
... AIC Mask Disable Command Register (AIC_MDCR) REGISTER ADDRESS AIC_MDCR 0xFFF8.2124 RESERVED 15 14 MDC15 MDC14 MDC13 7 6 MDC7 MDC6 MDC5 MDC x: Mask Disable Command effect 1 = Disables the corresponding interrupt channel W90N740CD/W90N740CDG R/W DESCRIPTION Mask Enable Command Register RESERVED MEC12 MEC11 MEC4 MEC3 ...
Page 169
... SSCx: Source Set Command effect Activates the corresponding interrupt channel AIC Source Clear Command Register (AIC_SCCR) REGISTER ADDRESS 0xFFF8.212C AIC_SCCR RESERVED 15 14 SCC15 SCC14 SCC13 7 6 SCC7 SCC7 SCC6 W90N740CD/W90N740CDG R/W DESCRIPTION W Source Set Command Register RESERVED SSC12 SSC11 SSC4 SSC3 R/W ...
Page 170
... For example, GPIO20 ~ GPIO17 can be programmed as external interrupt input pins, GPIO16 ~ GPIO15 for external DMA function, GPIO14 ~ GPIO13 for TIMER tone output, GPIO12 as the watchdog timeout flag, GPIO11 ~ GPIO10 used for UART console monitor, GPIO9 ~ GPIO4 for modem. The table as shown below is a summary. W90N740CD/W90N740CDG R/W DESCRIPTION W ...
Page 171
... GPIO2 GP2 GP1 GPIO1 GPIO0 GP0 Note: U means internal weak pull-up. 7.12.1 GPIO Controller Registers Map REGISTER ADDRESS GPIO_CFG 0xFFF8.3000 GPIO_DIR 0xFFF8.3004 GPIO_DATAOUT 0xFFF8.3008 GPIO_DATAIN 0xFFF8.300C DEBNCE_CTRL 0xFFF8.3010 W90N740CD/W90N740CDG MULTI-FUNCTION 1 TYPE NAME TYPE IO nIRQ3 IO nIRQ2 IO nIRQ1 IO nIRQ0 IO NXDREQ3 IO nXDACK IO TIMER1 IO TIMER0 ...
Page 172
... GPIOCFG18 [17:16]: Operating mode for GPIO18 11 GPIOCFG18 Name GPIO18 RESERVED OVRCUR is used as over current indicator if this field set to 10. nIRQ1 is one of the external interrupt input pins. W90N740CD/W90N740CDG R/W DESCRIPTION R/W GPIO Configuration Register 28 27 RESERVED 20 ...
Page 173
... STDBY is a USB IO port, which controls the external USB transceiver power-down mode. TIMER0 is the tone output of TIMER0. GPIOCFG12 [7:6]: Operating mode for GPIO12 11 GPIOCFG12 Name GPIO12 RESERVED nWDOG is the timeout output of Watch-Dog Timer. W90N740CD/W90N740CDG 10 Name Type Name RESERVED nIRQ0 10 Type Name ...
Page 174
... UART modem signal pins. GPIOCFG3_0 [1:0]: Operating mode for GPIO3, GPIO2, GPIO1, and GPIO0 11 GPIOCFG3_0 Name Type GPIO3 GPIO2 RESERVED GPIO1 GPIO0 GPIO Direction Register (GPIO_DIR) REGISTER ADDRESS 0xFFF8.3004 GPIO_DIR W90N740CD/W90N740CDG 11 10 Type Name Type O RESERVED O 10 Type Name Type Name nTOE O ...
Page 175
... GPIODO5 GPIODOx: GPIO output corresponding to bit x If the GPIOx is used as a general-purpose output pin, then the corresponding GPIODOx specifies the value to output from this pin. GPIO Data Input Register (GPIO_DATAIN) REGISTER ADDRESS GPIO_DATAIN 0xFFF8.3008 W90N740CD/W90N740CDG 28 27 RESERVED 20 19 GPIOD20 GPIOD19 12 11 ...
Page 176
... These three bits are used to select the clock rate for de-bouncer circuit. The relationship between the system clock HCLK and the de-bounce clock TCLK_BUN is as follows: DBE3 [3]: De-bouncer Circuit Enable for GPIO20 0 = De-bounce function is disabled 1 = De-bounce function is enabled W90N740CD/W90N740CDG 28 27 RESERVED 20 ...
Page 177
... Voltage on Any Pin ...............................................................…….......... Power Supply Voltage (Core logic) .............................…...........……….. Power Supply Voltage (IO Buffer) ...............................…...........……….. Injection Current (latch-up testing) ..............................................………. Crystal Frequency .............................................…...........………..……… W90N740CD/W90N740CDG - 174 - 0 ° °C -40 °C ~ 125°C -0. ...
Page 178
... Single Ended Receiver Threshold SE V Static Output Low Voltage OL V Static Output High Voltage OH V Output Signal Crossover Voltage CRS Z Driver Output Resistance DRV W90N740CD/W90N740CDG CONDITION Depend on driving Depend on driving F cpu = 80MHz F cpu = 80MHz 0.4 V CONDITIONS ⎜DP − DM⎥ ...
Page 179
... SYM [31:0] Setup Time DSU D [31:0] Hold Time [31:0], A [24:0], nSCS [1:0], SDQM [3:0], CKE, nSWE, nSRAS, nSCAS T DO 8.3.2 EBI/External Master Interface AC Characteristics MCLK EMREQ T EMACK W90N740CD/W90N740CDG 1.5V T DSU Input Valid DO Output Valid PARAMETER EMSU T EMH T EMAO - 176 - T DH 1.5V MIN ...
Page 180
... EMREQ Hold Time EMH T EMACK Output Delay Time EMAO 8.3.3 EBI/(ROM/SRAM/External I/O) AC Characteristics MCLK T NECSO nECS[3:0] T ADDO A[24:0] nOE D[31:0] nWAIT nWBE[3:0] D[31:0] W90N740CD/W90N740CDG DESCRIPTION Address Valid T NOEO T DSU T T NWASU NWAH T NWBO T DO Write Data Vaild - 177 - MIN. MAX. ...
Page 181
... SYM. DESCRIPTION T Rise Time (Full Speed Fall Time (Full Speed F Rise/Fall Time Matching (Full Speed) T RFM T Full Speed Data Rate DRATE W90N740CD/W90N740CDG DESCRIPTION Rise Tim e 90% Differential Data Lines 10 50pF Low Speed: 75ns 50pF, 300ns Data Signal Rise and Fall Time ...
Page 182
... RX_D [3:0] RX_DV RX_ERR SYMBOL DESCRIPTION T Transmit Output Delay Time TXO Receive Setup Time T RXSU Receive Hold Time T RXH MDC MDIO W90N740CD/W90N740CDG T TXO Valid Transmit Signal Timing Relationships at MII T RXSU VALID INPUT Receive Signal Timing Relationships at MII T T MDSU MDH VALID INPUT ...
Page 183
... SYMBOL DESCRIPTION MDIO Output Delay Time T MDO T MDIO Setup Time MDSU T MDIO Hold Time MDH W90N740CD/W90N740CDG lid MDIO Write to PHY Timing MIN 180 - MAX. UNIT ...
Page 184
... PACKAGE DIMENSIONS 176-Pin LQFP (note that the value in inches may have some inaccuracy translated from the value in millimeter) W90N740CD/W90N740CDG Publication Release Date: Aug. 18, 2005 - 181 - Revision A6 ...
Page 185
... EXT3CON 0xFFF0.1024 CKSKEW 0xFFF0.1F00 Cache Control Registers Map REGISTER ADDRESS CAHCNF 0xFFF0.2000 CAHCON 0xFFF0.2004 CAHADR 0xFFF0.2008 W90N740CD/W90N740CDG R/W DESCRIPTION R Product Identifier Register R/W Arbitration Control Register R/W PLL Control Register R/W Clock Select Register R/W DESCRIPTION R/W EBI control register ...
Page 186
... CAM12M_0 0xFFF0.3060 CAM12L_0 0xFFF0.3064 CAM13M_0 0xFFF0.3068 CAM13L_0 0xFFF0.306C CAM14M_0 0xFFF0.3070 CAM14L_0 0xFFF0.3074 W90N740CD/W90N740CDG R/W DESCRIPTION R/W CAM Command Register R/W CAM enable register R/W CAM1 Most Significant Word Register R/W CAM1 Least Significant Word Register R/W CAM2 Most Significant Word Register ...
Page 187
... RXDLSA_0 0xFFF0.30A0 DMARFC_0 0xFFF0.30A4 TSDR_0 0xFFF0.30A8 RSDR_0 0xFFF0.30AC FIFOTHD_0 0xFFF0.30B0 W90N740CD/W90N740CDG R/W DESCRIPTION R/W CAM15 Most Significant Word Register R/W CAM15 Least Significant Word Register R/W CAM16 Most Significant Word Register R/W CAM16 Least Significant Word Register R/W MAC Interrupt Enable Register ...
Page 188
... DMA REGISTERS DMARFS_0 0xFFF0.30C8 R/W DMA Receive Frame Status Register CTXDSA_0 0xFFF0.30CC CTXBSA_0 0xFFF0.30D0 CRXDSA_0 0xFFF0.30D4 CRXBSA_0 0xFFF0.30D8 W90N740CD/W90N740CDG DESCRIPTION R MAC Receive Pause count register R MAC Receive Pause Current Count Register R MAC Remote pause count register Current Transmit Descriptor Start Address ...
Page 189
... CAM11M_1 0xFFF0.3858 CAM11L_1 0xFFF0.385C CAM12M_1 0xFFF0.3860 CAM12L_1 0xFFF0.3864 CAM13M_1 0xFFF0.3868 CAM13L_1 0xFFF0.386C W90N740CD/W90N740CDG R/W DESCRIPTION R/W CAM Command Register R/W CAM enable register R/W CAM1 Most Significant Word Register R/W CAM1 Least Significant Word Register R/W CAM2 Most Significant Word Register ...
Page 190
... TXDLSA_1 0xFFF0.389C RXDLSA_1 0xFFF0.38A0 DMARFC_1 0xFFF0.38A4 TSDR_1 0xFFF0.38A8 RSDR_1 0xFFF0.38AC FIFOTHD_1 0xFFF0.38B0 W90N740CD/W90N740CDG R/W DESCRIPTION R/W CAM14 Most Significant Word Register R/W CAM14 Least Significant Word Register R/W CAM15 Most Significant Word Register R/W CAM15 Least Significant Word Register R/W CAM16 Most Significant Word Register ...
Page 191
... GDMA_DSTB1 0xFFF0.4028 R/W GDMA_TCNT1 0xFFF0.402C R/W GDMA_CSRC1 0xFFF0.4030 GDMA_CDST1 0xFFF0.4034 GDMA_CTCNT1 0xFFF0.4038 W90N740CD/W90N740CDG R/W DESCRIPTION R/W MAC Interrupt Status Register R/W MAC General Status Register R MAC Receive Pause count register R MAC Receive Pause Current Count Register R MAC Remote pause count register ...
Page 192
... HcRhDescriptorB 0xFFF0.504C HcRhStatus 0xFFF0.5050 HcRhPortStatus [1] 0xFFF0.5054 HcRhPortStatus [2] 0xFFF0.5058 W90N740CD/W90N740CDG R/W DESCRIPTION R Host Controller Revision Register R/W Host Controller Control Register R/W Host Controller Command Status Register R/W Host Controller Interrupt Status Register R/W Host Controller Interrupt Enable Register R/W Host Controller Interrupt Disable Register ...
Page 193
... NATCFG63 0xFFF0.61FC R/W NAT Entry 63 Configuration Register EXMACM 0xFFF0.6200 EXMACL 0xFFF0.6204 INMACM 0xFFF0.6208 INMACL 0xFFF0.620C R/W W90N740CD/W90N740CDG R/W DESCRIPTION R/W NAT Command Register W NAT Counter 0 Clear Register W NAT Counter 1 Clear Register W NAT Counter 2 Clear Register W NAT Counter 3 Clear Register R/W NAT Entry 0 Configuration Register R/W NAT Entry 1 Configuration Register ...
Page 194
... LSMAC63M 0xFFF0.6FF0 LSMAC63L 0xFFF0.6FF4 RSMAC63M 0xFFF0.6FF8 RSMAC63L 0xFFF0.6FFC W90N740CD/W90N740CDG R/W DESCRIPTION R/W NAT Masquerading IP Address Entry 0 R/W NAT Masquerading Port Number Entry 0 R/W Local Station IP Address Entry 0 R/W Local Station Port Number Entry 0 Local Station MAC Address Most Significant R/W ...
Page 195
... GPIO Controller Registers Map REGISTER ADDRESS GPIO_CFG 0xFFF8.3000 GPIO_DIR 0xFFF8.3004 GPIO_DATAOUT 0xFFF8.3008 GPIO_DATAIN 0xFFF8.300C DEBNCE_CTRL 0xFFF8.3010 W90N740CD/W90N740CDG DESCRIPTION R Receive Buffer Register (DLAB = 0) W Transmit Holding Register (DLAB = 0) Interrupt Enable Register (DLAB = 0) Divisor Latch Register (LS) (DLAB = 1) Divisor Latch Register (MS) (DLAB = 1) R Interrupt Identification Register ...
Page 196
... AIC_IMR 0xFFF8.2114 AIC_OISR 0xFFF8.2118 AIC_MECR 0xFFF8.2120 AIC_MDCR 0xFFF8.2124 AIC_SSCR 0xFFF8.2128 AIC_SCCR 0xFFF8.212C AIC_EOSCR 0xFFF8.2130 W90N740CD/W90N740CDG R/W DESCRIPTION R/W Source Control Register 1 R/W Source Control Register 2 R/W Source Control Register 3 R/W Source Control Register 4 R/W Source Control Register 5 R/W Source Control Register 6 ...
Page 197
... DATE A1 Jan 15, 2003 A2 May 27, 2003 A3 Sep. 3, 2004 A4 Nov. 26, 2004 A5 April 19, 2005 A6 Aug. 18, 2005 W90N740CD/W90N740CDG PACKAGE DESCRIPTION 176 Leads, body 1.4 mm 176 Leads, body 1.4 mm, Lead free package PAGE - Initial Issued - Add DC specifications in 8.2 Change Pin Description Page 54 Change tCOH description Page 56 Remove Fig ...
Page 198
... Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. W90N740CD/W90N740CDG Important Notice Publication Release Date: Aug. 18, 2005 - 195 - ...