W90N740CDG Nuvoton Technology Corporation of America, W90N740CDG Datasheet - Page 120

• Manufacturer Part Number: W90N740CDG
• Description: IC MCU ARM7 TDMI 176-LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W90r

Specifications of W90N740CDG

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, Ethernet, UART/USART, USB
• Peripherals: DMA, POR, WDT
• Number Of I /o: 21
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

DAFIX [6]: Destination Address Fixed
0 = Destination address is changed during the GDMA operation
1 = Do not change the destination address during the GDMA operation. This feature can be used
DADIR [5]: Source Address Direction
0 = Source address is incremented successively
1 = Source address is decremented successively
DADIR [4]: Destination Address Direction
0 = Destination address is incremented successively
1 = Destination address is decremented successively
GDMAMS [3:2]: GDMA Mode Select
00 = Software mode (memory-to-memory)
01 = External nXDREQ1/2/3 mode for external device
10 = Reserved
11 = Reserved
GDMAEN [0]: GDMA Enable
0 = Disables the GDMA operation
1 = Enables the GDMA operation; this bit will be clear automatically when the transfer is complete on
Channel 0/1 Source Base Address Register (GDMA_SRCB0, GDMA_SRCB1)
The GDMA channel starts reading its data from the source address as defined in this source base
address register.
GDMA_SRCB0 0xFFF0.4004 R/W Channel 0 Source Base Address Register
GDMA_SRCB1 0xFFF0.4024 R/W Channel 1 Source Base Address Register
REGISTER
when data were transferred from multiple sources to a single destination.
AUTOIEN [19] register bit is on Disable mode.
31
23
15
7
ADDRESS
30
22
14
6
29
21
13
R/W
5
SRC_BASE_ADDR [31:24]
SRC_BASE_ADDR [23:16]
SRC_BASE_ADDR [15:8]
SRC_BASE_ADDR [7:0]
28
20
12
4
- 117 -
W90N740CD/W90N740CDG
DESCRIPTION
27
19
11
3
Publication Release Date: Aug. 18, 2005
26
18
10
2
25
17
9
1
RESET VALUE
0x0000.0000
0x0000.0000
Revision A6
24
16
8
0