W90N740CDG Nuvoton Technology Corporation of America, W90N740CDG Datasheet - Page 119

• Manufacturer Part Number: W90N740CDG
• Description: IC MCU ARM7 TDMI 176-LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W90r

Specifications of W90N740CDG

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, Ethernet, UART/USART, USB
• Peripherals: DMA, POR, WDT
• Number Of I /o: 21
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

DM [15]: Demand Mode
0 = Normal external GDMA mode
1 = When this bit is set to 1, the external GDMA operation is speeded up. When external GDMA
TWS [13:12]: Transfer Width Select
00 = One byte (8 bits) is transferred for every GDMA operation
01 = One half-word (16 bits) is transferred for every GDMA operation
10 = One word (32 bits) is transferred for every GDMA operation
11 = Reserved
The GDMA_SCRB and GDMA_DSTB should be alignment under the TWS selection
SBMS [11]: Single/Block Mode Select
0 = Selects single mode. It requires an external GDMA request for every incurring GDMA operation.
1 = Selects block mode. It requires a single external GDMA request during the atomic GDMA
7.7.2.1. BME [9]: Burst Mode Enable
0 = Disables the 4-data burst mode
1 = Enables the 4-data burst mode
Ff there are 16 words to be transferred, and BME [9]=1, the GDMA_TCNT should be 0x04;
However, if BME [9]=0, the GDMA_TCNT should be 0x10.
SIEN [8]: Stop Interrupt Enable
0 = Do not generate an interrupt when the GDMA operation is stopped
1 = interrupt is generated when the GDMA operation is stopped
SAFIX [7]: Source Address Fixed
0 = Source address is changed during the GDMA operation
1 = Do not change the destination address during the GDMA operation. This feature can be used
device is operating in the demand mode, the GDMA transfers data as long as the external GDMA
request signal nXDREQ1/2/3 is active. The amount of data transferred depends on how long the
nXDREQ1/2/3 is active. When the nXDREQ1/2/3 is active and GDMA gets the bus in Demand
mode, DMA holds the system bus until the nXDREQ1/2/3 signal becomes non-active. Therefore,
the period of the active nXDREQ1/2/3 signal should be carefully tuned such that the entire
operation does not exceed an acceptable interval (for example, in a DRAM refresh operation).
operation. An atomic GDMA operation is defined as the sequence of GDMA operations until the
transfer count register reaches zero.
when data were transferred from a single source to multiple destinations.
- 116 -
W90N740CD/W90N740CDG