W90N740CDG Nuvoton Technology Corporation of America, W90N740CDG Datasheet - Page 118

• Manufacturer Part Number: W90N740CDG
• Description: IC MCU ARM7 TDMI 176-LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W90r

Specifications of W90N740CDG

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, Ethernet, UART/USART, USB
• Peripherals: DMA, POR, WDT
• Number Of I /o: 21
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

SABNDERR [22]: Source address Boundary alignment Error flag
If TWS [13:12]=10, GDMA_SRCB [1:0] should be 00
If TWS [13:12]=01, GDMA_SRCB [0] should be 0
The address boundary alignment should be depended on TWS [13:12].
0 = the GDMA_SRCB is on the boundary alignment.
1 = the GDMA_SRCB not on the boundary alignment
The SABNDERR register bits just can be read only.
DABNDERR [21]: Destination address Boundary alignment Error flag
If TWS [13:12]=10, GDMA_DSTB [1:0] should be 00
If TWS [13:12]=01, GDMA_DSTB [0] should be 0
The address boundary alignment should be depended on TWS [13:12].
0 = the GDMA_DSTB is on the boundary alignment.
1 = the GDMA_DSTB not on the boundary alignment
The DABNDERR register bits just can be read only.
GDMATERR [20]: GDMA Transfer Error
O = No error occurs
1 = Hardware sets this bit on a GDMA transfer failure
Transfer error will generate GDMA interrupt
AUTOIEN [19]: Auto initialization Enable
0 = Disables auto initialization
1 = Enables auto initialization, the GDMA_CSRC0/1,GDMA_CDST0/1,and GDMA_CTCNT0/1 registers
TC [18]: Terminal Count
0 = Channel does not expire
1 = Channel expires; this bit is set only by GDMA hardware, and clear by software to write logic 0.
TC [18] is the GDMA interrupt flag. TC [18] or GDMATERR[20] will generate interrupt
BLOCK [17]: Bus Lock
0 = Unlocks the bus during the period of transfer
1 = locks the bus during the period of transfer
SOFTREQ [16]: Software Triggered GDMA Request
Software can request the GDMA transfer service by setting this bit to 1. This bit is automatically
cleared by hardware when the transfer is completed. This bit is available only while GDMAMS [3:2]
register bits are set on software mode (memory to memory).
are updated by the GDMA_SRC0/1,GDMA_DST0/1,and GDMA_TCNT0/1 registers automatically
when transfer is complete.
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W90N740CD/W90N740CDG
Publication Release Date: Aug. 18, 2005
Revision A6