W90N740CDG Nuvoton Technology Corporation of America, W90N740CDG Datasheet - Page 150

• Manufacturer Part Number: W90N740CDG
• Description: IC MCU ARM7 TDMI 176-LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W90r

Specifications of W90N740CDG

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, Ethernet, UART/USART, USB
• Peripherals: DMA, POR, WDT
• Number Of I /o: 21
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

W90N740CD/W90N740CDG
Line Status Control Register (LSR)
Register
Address
R/W
Description
Reset Value
0xFFF8.0014
R
Line Status Register
0x6060.6060
LSR
7
6
5
4
3
2
1
0
ERR_RX
TE
THRE
BII
FEI
PEI
OEI
RFDR
ERR_RX [7]: RX FIFO Error
0 = RX FIFO works normally
1 = There is at least one parity error (PE), framing error (FE), or break indication (BI) in the FIFO.
ERR_RX is cleared when CPU reads the LSR and if there are no subsequent errors in the RX FIFO.
TE [6]: Transmitter Empty
0 = Either Transmitter Holding Register (THR - TX FIFO) or Transmitter Shift Register (TSR) are not
empty.
1 = Both THR and TSR are empty.
THRE [5]: Transmitter Holding Register Empty
0 = THRE is not empty.
1 = THRE is empty.
THRE is set when the last data word of TX FIFO is transferred to Transmitter Shift Register (TSR). The
CPU resets this bit when the THR (or TX FIFO) is loaded. This bit also causes the UART to issue an
interrupt (Irpt_THRE) to the CPU when IER [1]=1.
BII [4]: Break Interrupt Indicator
This bit is set to a logic 1 whenever the received data input is held in the "spacing state" (logic 0) for
longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits)
and is reset whenever the CPU reads the contents of the LSR.
FEI [3]: Framing Error Indicator
This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop
bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU reads
the contents of the LSR.
Publication Release Date: Aug. 18, 2005
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Revision A6