W90N740CDG Nuvoton Technology Corporation of America, W90N740CDG Datasheet - Page 92

• Manufacturer Part Number: W90N740CDG
• Description: IC MCU ARM7 TDMI 176-LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W90r

Specifications of W90N740CDG

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, Ethernet, UART/USART, USB
• Peripherals: DMA, POR, WDT
• Number Of I /o: 21
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

RXDLSA [31:0]: DMA receive descriptor link list start address
Default value: 0xFFFF.FFFC
This register defines the receive descriptor link list start address for frame reception process. While
software first turn on RxDMA after the hardware reset or software reset, the content of this register will
be loaded into the current receive descriptor start address. The value of this register will not be
updated during any hardware operation. The system would ignore the least 2 significant bits to fit word
alignment.
DMA Receive Frame Control Register (DMARFC_0, DMARFC_1)
RXMS [15:0]: DMA receive frame maximum size
Default value: 0800h
This value controls the maximum bytes for a received frame can be saved to memory. If the received
frame size exceeds the value stored in this location and the EnDFO is set, an error interrupt is
reported. The default maximum size is 2K bytes.
DMARFC_0
DMARFC_1
REGISTER
31
23
15
7
0xFFF0.30A4
0xFFF0.38A4
ADDRESS
30
22
14
6
29
21
13
5
R/W
R/W
R/W
DMA Receive Frame Control Register
DMA Receive Frame Control Register
28
20
12
4
Reserved
Reserved
RXMS
RXMS
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W90N740CD/W90N740CDG
DESCRIPTION
27
19
11
3
Publication Release Date: Aug. 18, 2005
26
18
10
2
25
17
9
1
RESET VALUE
0x0000.0800
0x0000.0800
Revision A6
24
16
8
0