W90N740CDG Nuvoton Technology Corporation of America, W90N740CDG Datasheet - Page 66

• Manufacturer Part Number: W90N740CDG
• Description: IC MCU ARM7 TDMI 176-LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W90r

Specifications of W90N740CDG

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, Ethernet, UART/USART, USB
• Peripherals: DMA, POR, WDT
• Number Of I /o: 21
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

LDLK [4] ：Load and Lock I-Cache/D-Cache
Loads the instruction or data from external memory and locks into cache. Both WAY and ADDR bits in
CAHADR register must be specified.
FLHS [3] ：Flush I-Cache/D-Cache single line
Flushes the entire I-Cache/D-Cache per line. Both WAY and ADDR bits in CAHADR register must be
specified.
FLHA [2] ：Flush I-Cache/D-Cache entirely
To flush the entire I-Cache/D-Cache, also flushes any locked-down code. If the I-Cache/D-Cache
contains locked down code, the programmer must flush lines individually.
DCAH [1] ：D-Cache selected
When set to “1”, the command set is executed with D-Cache.
ICAH [0] ：I-Cache selected
When set to “1”, the command set is executed with I-Cache.
Notes：When using the FLHA or ULKA command, you can set both ICAH and DCAH bits to execute
entire I-Cache and D-Cache flushing or unlocking. But, FLHS and ULKS commands can only be
executed with a cache line specified by CAHADR register in I-Cache or D-Cache at a time. If you set
both ICAH and DCAH bits, and set FLHS or ULKS command bit, it will be treated as an invalid
command and no operation is done and the command terminates with no exception.
The Drain Write Buffer operation is only for D-Cache. To perform this operation, you must set DRWB
and DCAH bits. If the ICAH bit is set when using DRWB command, it will be an invalid command and no
operation is done and the command terminates with no exception.
Cache Address Register (CAHADR)
W90N740 Cache Controller supports one address register. This address register is used with the
command set in the control register (CAHCON) by specifying instruction/data address.
REGISTER
CAHADR
WAY
31
23
15
7
0xFFF0.2008
ADDRESS
30
22
14
6
29
21
13
5
R/W
R/W Cache address register
28
20
12
4
ADDR
ADDR
ADDR
- 63 -
W90N740CD/W90N740CDG
ADDR
DESCRIPTION
27
19
11
3
Publication Release Date: Aug. 18, 2005
26
18
10
2
25
17
9
1
RESET VALUE
0x0000.0000
Revision A6
24
16
8
0