HD64F3694FY Renesas Electronics America, HD64F3694FY Datasheet - Page 189

IC H8 MCU FLASH 32K 48-LQFP

HD64F3694FY

Manufacturer Part Number
HD64F3694FY
Description
IC H8 MCU FLASH 32K 48-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet

Specifications of HD64F3694FY

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
29
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3694FYJV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
HD64F3694FYV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Legend:
Note:
12.3.3
TIERW controls the timer W interrupt request.
Bit
0
Bit
7
6 to 4
3
2
1
0
*
Bit Name
TOA
Bit Name
OVIE
IMIED
IMIEC
IMIEB
IMIEA
Timer Interrupt Enable Register W (TIERW)
The change of the setting is immediately reflected in the output value.
X: Don't care.
0
0
0
0
Initial
Value
0
Initial
Value
0
All 1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Timer Output Level Setting A
Sets the output value of the FTIOA pin until the first
compare match A is generated.
0: Output value is 0*
1: Output value is 1*
Description
Timer Overflow Interrupt Enable
When this bit is set to 1, FOVI interrupt requested by OVF
flag in TSRW is enabled.
Reserved
These bits are always read as 1.
Input Capture/Compare Match Interrupt Enable D
When this bit is set to 1, IMID interrupt requested by
IMFD flag in TSRW is enabled.
Input Capture/Compare Match Interrupt Enable C
When this bit is set to 1, IMIC interrupt requested by
IMFC flag in TSRW is enabled.
Input Capture/Compare Match Interrupt Enable B
When this bit is set to 1, IMIB interrupt requested by
IMFB flag in TSRW is enabled.
Input Capture/Compare Match Interrupt Enable A
When this bit is set to 1, IMIA interrupt requested by
IMFA flag in TSRW is enabled.
Rev.5.00 Nov. 02, 2005 Page 159 of 418
Section 12 Timer W
REJ09B0028-0500

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