HD64F3694FY Renesas Electronics America, HD64F3694FY Datasheet - Page 76
![IC H8 MCU FLASH 32K 48-LQFP](/photos/28/61/286105/48-lqfp__plqp0048kc-a_sml.jpg)
HD64F3694FY
Manufacturer Part Number
HD64F3694FY
Description
IC H8 MCU FLASH 32K 48-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.HD64F3694GFYV.pdf
(452 pages)
Specifications of HD64F3694FY
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
29
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3694FYJV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Company:
Part Number:
HD64F3694FYV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 2 CPU
Bit Manipulation in a Register Containing a Write-Only Bit
Example 3: BCLR instruction executed designating port 5 control register PCR5
P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at
P56. P55 to P50 are output pins that output low-level signals. An example of setting the P50 pin as
Rev.5.00 Nov. 02, 2005 Page 46 of 418
REJ09B0028-0500
Input/output
Pin state
PCR5
PDR5
RAM0
Input/output
Pin state
PCR5
PDR5
RAM0
MOV.B
MOV.B
MOV.B
BSET
MOV.B
MOV.B
Prior to executing BSET instruction
BSET instruction executed
After executing BSET instruction
#80,
R0L,
R0L,
#0,
@RAM0, R0L
R0L,
P57
Input
Low
level
0
1
1
P57
Input
Low
level
0
1
1
R0L
@RAM0
@PDR5
@PDR5
@RAM0
P56
Input
High
level
0
0
0
P56
Input
High
level
0
0
0
P55
Output
Low
level
1
0
0
P55
Output
Low
level
1
0
0
The PDR5 value (H'80) is written to a work area in
memory (RAM0) as well as to PDR5.
The BSET instruction is executed designating the PDR5
work area (RAM0).
The work area (RAM0) value is written to PDR5.
P54
Output
Low
level
1
0
0
P54
Output
Low
level
1
0
0
P53
Output
Low
level
1
0
0
P53
Output
Low
level
1
0
0
P52
Output
Low
level
1
0
0
P52
Output
Low
level
1
0
0
P51
Output
1
0
0
P51
Output
1
0
0
Low
level
Low
level
P50
Output
Low
level
1
0
0
P50
Output
High
level
1
1
1
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