HD64F3694FY Renesas Electronics America, HD64F3694FY Datasheet - Page 286
![IC H8 MCU FLASH 32K 48-LQFP](/photos/28/61/286105/48-lqfp__plqp0048kc-a_sml.jpg)
HD64F3694FY
Manufacturer Part Number
HD64F3694FY
Description
IC H8 MCU FLASH 32K 48-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.HD64F3694GFYV.pdf
(452 pages)
Specifications of HD64F3694FY
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
29
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3694FYJV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Company:
Part Number:
HD64F3694FYV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 286 of 452
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Section 15 I
Receive Operation
In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when
MST in ICCR1 is 1, and is input when MST is 0. For receive mode operation timing, refer to
figure 15.15. The reception procedure and operations in receive mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial
2. When the transfer clock is output, set MST to 1 to start outputting the receive clock.
3. When the receive operation is completed, data is transferred from ICDRS to ICDRR and
4. To stop receiving when MST = 1, set RCVD in ICCR1 to 1, then read ICDRR. Then, SCL is
Rev.5.00 Nov. 02, 2005 Page 256 of 418
REJ09B0028-0500
processing
(Output)
ICDRS
ICDRT
TDRE
SDA
SCL
TRS
User
setting)
RDRF in ICSR is set. When MST = 1, the next byte can be received, so the clock is
continually output. The continuous reception is performed by reading ICDRR every time
RDRF is set. When the 8th clock is risen while RDRF is 1, the overrun is detected and
AL/OVE in ICSR is set. At this time, the previous reception data is retained in ICDRR.
fixed high after receiving the next byte data.
[2] Set TRS
2
C Bus Interface 2 (IIC2)
[3] Write data
to ICDRT
Data 1
Bit 0
Figure 15.14 Transmit Mode Operation Timing
1
[3] Write data
to ICDRT
Bit 1
2
Data 1
Bit 6
7
Data 2
Bit 7
8
Bit 0
Data 2
1
Bit 6
7
[3] Write data
Bit 7
to ICDRT
8
Data 3
[3] Write data
Data 3
Bit 0
to ICDRT
1
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