HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 211

• Manufacturer Part Number: HD6417020SVX12I
• Description: IC SUPERH MPU ROMLESS 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SVX12I

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 12.5MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Address Modes:
• Single Address Mode
192 RENESAS
Note:
In the single address mode, both the transfer source and destination are external; one
(selectable) is accessed by a DACK signal while the other is accessed by an address. In this
mode, the DMAC performs the DMA transfer in 1 bus cycle by simultaneously outputting a
transfer request acknowledge DACK signal to one external device to access it while outputting
an address to the other end of the transfer. Figure 9.6 shows an example of a transfer between
an external memory and an external device with DACK in which the external device outputs
data to the data bus while that data is written in external memory in the same bus cycle.
Two types of transfers are possible in the single address mode: 1) transfers between external
devices with DACK and memory-mapped external devices, and 2) transfers between external
devices with DACK and external memory. The only transfer requests for either of these is the
external request (DREQ). Figure 9.7 shows the DMA transfer timing for the single address
mode.
The read/write direction is decided by the RS3-RS0 bits of the CHCRn registers. If RS3-
RS0=0010, the direction is shown as case 1 (circled number above); if RS3-RS0=0010,
the direction is shown as case 2. Also, DACK output (when writing) indicates case 2.
SH microcomputer
Figure 9.6 Data Flow in Single Address Mode
External address bus
DMAC
: Data flow
DREQ
DACK
External data bus
Read
(1) (2)
*
Write
*
External device
with DACK
External
memory