HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 326

IC SUPERH MPU ROMLESS 100TQFP

HD6417020SVX12I

Manufacturer Part Number
HD6417020SVX12I
Description
IC SUPERH MPU ROMLESS 100TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet

Specifications of HD6417020SVX12I

Core Processor
SH-1
Core Size
32-Bit
Speed
12.5MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

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Manufacturer
Quantity
Price
Part Number:
HD6417020SVX12I
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Part Number:
HD6417020SVX12IV
Manufacturer:
RENESAS
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HD6417020SVX12IV
Manufacturer:
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Quantity:
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Note: Bits set to TPC output by NDERA or NDERB are read-only.
11.2.3
NDRA is an eight-bit read/write register that stores the next output data for TPC output groups 1
and 0 (TP7–TP0). When used for TPC output, the contents of the NDRA are transferred to the
corresponding PBDR bits when the ITU compare match specified in the TPC output control
register TPCR occurs.
The address of the NDRA differs depending on whether TPCR settings select the same trigger or
different triggers for TPC output groups 1 and 0. When reset, NDRA is initialized to H'00. It is not
initialized by standby mode.
Same Trigger for TPC Output Groups 1 and 0: If TPC output groups 1 and 0 are triggered by
the same compare match, the address of the NDRA is H'FFFFF5. The 4 upper bits becomes group
1 and the 4 lower bits become group 0. Address H'5FFFFF7 in such cases consists entirely of
reserved bits. These bits cannot be modified and always read as 1.
Address H'5FFFFF5:
• Bits 7–4 (next data 7–4 (NDR7–NDR4)): NDR7-NDR4 store the next output data for TPC
• Bits 3–0 (next data 3–0 (NDR3–NDR0)): NDR3-NDR0 store the next output data for TPC
308 RENESAS
output group 1.
output group 0.
Initial value:
Initial value:
Bit name:
Bit name:
Next Data Register A (NDRA)
R/W:
R/W:
Bit:
Bit:
PB7DR
R/(W)*
NDR7
R/W
7
0
7
0
PB6DR PB5DR
R/(W)*
NDR6
R/W
6
0
6
0
R/(W)*
NDR5
R/W
5
0
5
0
PB4DR PB3DR
R/(W)*
NDR4
R/W
4
0
4
0
R/(W)*
NDR3
R/W
3
0
3
0
PB2DR
R/(W)*
NDR2
R/W
2
0
2
0
PB1DR PB0DR
R/(W)*
NDR1
R/W
1
0
1
0
R/(W)*
NDR0
R/W
0
0
0
0

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