HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 78

• Manufacturer Part Number: HD6417020SVX12I
• Description: IC SUPERH MPU ROMLESS 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SVX12I

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 12.5MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

4.5.3
An instruction located immediately after a delayed branch instruction is called an “instruction
placed in a delay slot.” If an undefined instruction is located in a delay slot, illegal slot instruction
exception processing begins executing when the undefined code is decoded. Illegal slot instruction
exception processing also begins when the instruction located in the delay slot is an instruction
that rewrites the program counter. In this case, exception processing begins when the instruction
that rewrites the PC is decoded. The CPU performs illegal slot exception processing as follows:
1. Saves the status register onto the stack.
2. Pushes the program counter value onto the stack. The PC value saved is the branch destination
3. Fetches an exception processing service routine start address from the vector table
4.5.4
If an undefined instruction located other than a delay slot (immediately after a delayed branch
instruction) is decoded, general illegal instruction exception processing is executed. The CPU
follows the same procedure as for illegal slot exception processing, except that the program
counter (PC) value pushed on the stack in general illegal instruction exception processing is the
top address of the illegal instruction with the undefined code.
56 RENESAS
address of the delayed branch instruction immediately before the instruction that contains the
undefined code or rewrites the PC.
corresponding to the exception that occurred, branches to that address and the program starts
executing. The branch is not a delayed branch.
Illegal Slot Instruction
General Illegal Instructions