HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 34

• Manufacturer Part Number: HD6417020SVX12I
• Description: IC SUPERH MPU ROMLESS 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SVX12I

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 12.5MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Table 1.3
Type
Bus
control
(cont)
DMAC
16-bit
integrated-
timer pulse
unit (ITU)
Symbol
RAS
CASH
CASL
RD
WRH
WRL
CS0–CS7
AH
HBS, LBS 20, 56
WR
DREQ0,
DREQ1
DACK0,
DACK1
TIOCA0,
TIOCB0
TIOCA1,
TIOCB1
TIOCA2,
TIOCB2
TIOCA3,
TIOCB3
TIOCA4,
TIOCB4
Pin Functions (cont)
Pin No.
52
47
49
57
56
55
46–49,
51–54
61
55
66, 68
65, 67
51, 53
62, 64
83, 84
85, 86
87, 89
I/O
O
O
O
O
O
O
O
O
O
O
I
O
I/O
I/O
I/O
I/O
I/O
Name and Function
Row address strobe: DRAM row-address strobe-timing
signal.
Column address strobe high: DRAM column-address
strobe-timing signal outputs low level to access the
upper eight data bits.
Column address strobe low: DRAM column-address
strobe-timing signal outputs low level to access the
lower eight data bits.
Read: Indicates reading of data from an external device.
Upper write: Indicates write access to the upper eight
bits of an external device.
Lower write: Indicates write access to the lower eight
bits of an external device.
Chip select 0–7: Chip select signals for accessing
external memory and devices.
Address hold: Address hold timing signal for a device
using a multiplexed address/data bus.
Upper/lower byte strobe: Upper and lower byte strobe
signals. (Also used as WRH and A0.)
Write: Brought low during write access. (Also used as
WRL.)
DMA transfer request (channels 0 and 1): Input pins for
external DMA transfer requests.
DMA transfer acknowledge (channels 0 and 1):
Indicates that DMA transfer is acknowledged.
ITU input capture/output compare (channel 0): Input
capture or output compare pins.
ITU input capture/output compare (channel 1): Input
capture or output compare pins.
ITU input capture/output compare (channel 2): Input
capture or output compare pins.
ITU input capture/output compare (channel 3): Input
capture or output compare pins.
ITU input capture/output compare (channel 4): Input
capture or output compare pins.
RENESAS 11