R5F21226JFP#U0 Renesas Electronics America, R5F21226JFP#U0 Datasheet - Page 100
![IC R8C/22 MCU FLASH 48LQFP](/photos/28/61/286102/48-lqfp__plqp0048kb-a_sml.jpg)
R5F21226JFP#U0
Manufacturer Part Number
R5F21226JFP#U0
Description
IC R8C/22 MCU FLASH 48LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/22r
Datasheet
1.R5F21237DFPU0.pdf
(551 pages)
Specifications of R5F21226JFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
For Use With
R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21226JFP#U0R5F21226JFP#U1
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
R5F21226JFP#U0R5F21226JFP#V0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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- Download datasheet (6Mb)
R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 10.8
CAN0 Clock Select Register
b7 b6 b5 b4 b3 b2 b1
NOTES:
1.
2.
3.
Set the PRC0 bit in the PRCR register to 1 (enables w riting) before rew riting to the CCLKR register.
Set to the CCLK2, CCLK1, CCLK0 bits, only w hen the Reset bit in the C0CTLR register is 1 (reset/initialization mode).
When set the CCLK3 bit to 1 (CAN0 CPU interface operating), set to the Sleep bit in the C0CTLR register to 1 before
setting the CCLK3 bit.
CCLKR Register
b0
Bit Symbol
(b7-b4)
Symbol
CCLKR
CCLK0
CCLK1
CCLK2
CCLK3
Page 78 of 501
—
(1)
CAN0 clock select bits
CAN0 CPU interface sleep bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Address
Bit Name
135Fh
(2)
(3)
b2 b1 b0
0 0 0 : No division
0 0 1 : Divide-by-2 mode
0 1 0 : Divide-by-4 mode
0 1 1 : Divide-by-8 mode
1 0 0 : Divide-by-16 mode
1 0 1 :
1 1 0 :
1 1 1 :
0 : CAN0 CPU interface operating
1 : CAN0 CPU interface in sleep
Do not set
After Reset
Function
00h
10. Clock Generation Circuit
RW
RW
RW
RW
RW
—
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