R5F21226JFP#U0 Renesas Electronics America, R5F21226JFP#U0 Datasheet - Page 338
![IC R8C/22 MCU FLASH 48LQFP](/photos/28/61/286102/48-lqfp__plqp0048kb-a_sml.jpg)
R5F21226JFP#U0
Manufacturer Part Number
R5F21226JFP#U0
Description
IC R8C/22 MCU FLASH 48LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/22r
Datasheet
1.R5F21237DFPU0.pdf
(551 pages)
Specifications of R5F21226JFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
For Use With
R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21226JFP#U0R5F21226JFP#U1
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
R5F21226JFP#U0R5F21226JFP#V0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 338 of 551
- Download datasheet (6Mb)
R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
16.2.6.2
Figure 16.19 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation during Data
Transmission (4-Wire Bus Communication Mode). During the data transmit, the clock synchronous serial I/O
with chip select operates as described below.
When the clock synchronous serial I/O with chip select is set as a master device, it outputs a synchronous clock
and data. When the UUSA is set as a slave device, it outputs data in synchronized with the input clock while
“L” applies to the SCS pin.
When writing the transmit data to the SSTDR register after setting the TE bit to 1 (enables transmit), the TDRE
bit is automatically set to 0 (data is not transferred from the SSTDR to SSTRSR registers) and the data is
transferred from the SSTDR to SSTRSR registers. After the TDRE bit is set to 1 (data is transferred from the
SSTDR to SSTRSR registers), a transmit is started. When the TIE bit in the SSER register is set to 1, the TXI
interrupt request is generated.
When the 1-frame data is transferred while the TDRE bit is set to 0, the data is transferred from the SSTDR to
SSTRSR registers and the next frame transmit is started. If the 8th bit is transmitted while the TDRE is set to 1,
the TEND in the SSSR register is set to 1 (when the last bit of the transmit data is transmitted, the TDRE bit is
set to 1) and the state is retained. If the TEIE bit in the SSER register is set to 1 (enables transmit-end interrupt
request), the TEI interrupt request is generated. The SSCK pin is retained “H” after transmit-end and the SCS
pin is held “H”. When the SCS pin is transmitted When transmitting continuously while the SCS pin is held
“L”, write the next transmit data to the SSTDR register before transmitting the 8th bit.
Transmit can not be performed while the ORER bit in the SSSR register is set to 1 (overrun error occurs).
Confirm that the ORER bit is set to 0 before transmit.
The difference from the clock synchronous communication mode is that the SSO pin is placed in high-
impedance state while the SCS pin is placed in high-impedance state when operating as a master device and the
SSI pin is placed in high-impedance state while the SCS pin is placed in “H” input state when operating as a
slave device.
A sample flowchart is the same as the clock synchronous communication mode (refer to Figure 16.14 Sample
Flowchart of Data Transmission (Clock Synchronous Communication Mode)).
Data Transmission
Page 316 of 501
16. Clock Synchronous Serial Interface
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