R5F21226JFP#U0 Renesas Electronics America, R5F21226JFP#U0 Datasheet - Page 86
![IC R8C/22 MCU FLASH 48LQFP](/photos/28/61/286102/48-lqfp__plqp0048kb-a_sml.jpg)
R5F21226JFP#U0
Manufacturer Part Number
R5F21226JFP#U0
Description
IC R8C/22 MCU FLASH 48LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/22r
Datasheet
1.R5F21237DFPU0.pdf
(551 pages)
Specifications of R5F21226JFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
For Use With
R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21226JFP#U0R5F21226JFP#U1
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
R5F21226JFP#U0R5F21226JFP#V0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Table 7.32
X: 0 or 1
NOTES:
Table 7.33
X: 0 or 1
NOTE:
Table 7.34
Table 7.35
NOTE:
Table 7.36
NOTE:
Register
Register
Register
Setting
Setting
Setting
Register
Register
Setting
Setting
value
value
value
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
2. N-channel open drain output by setting the CSOS bit in the SSMR2 register to 1 when this pin functions as output.
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
1. Pulled up by setting the PU10 bit in the PUR0 register to 1.
1. Pulled up by setting the PU11 bit in the PUR0 register to 1.
value
value
Bit
Bit
Bit
Bit
Bit
PD3_5
PD3_7
PD3
PD3
X
X
X
0
0
1
1
X
X
X
0
0
1
1
Port P3_5/SCL/SSCK
Port P3_7/SSO
Port P4_2/VREF
Port P4_3
Port P4_4
ADCON1
Clock Synchronous Serial I/O with Chip Select
PD4_3
PD4_4
SSCK output control
VCUT
Clock Synchronous Serial I/O with Chip Select
(Refer to Table 16.4 Association between
PD4
PD4
SSO output control
(Refer to Table 16.4 Association between
Communication Modes and I/O Pins.)
0
1
0
1
0
1
Communication Modes and I/O Pins.)
Page 64 of 501
0
0
0
0
0
1
1
X
X
0
0
0
1
1
Input port
Input port/VREF input
Input port
Output port
Input port
Output port
SSCK input control
SSO input control
(1)
(1)
0
0
0
0
1
0
0
X
X
0
0
1
0
0
IICSEL
PMR
SSMR2
SOOS
0
X
0
X
0
0
1
X
X
0
0
0
0
1
ICCR1
ICE
Function
Function
Function
X
X
0
0
0
0
1
IICSEL
PMR
0
1
0
1
0
0
0
Input port
Output port
SSCK input
SSCK output
SCL input/output
Input port
Output port
SSO input
SSO output (CMOS output)
SSO output (N-channel open-drain
output)
(1)
7. Programmable I/O Ports
(2)
(2)
(1)
Function
Function
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