R5F21226JFP#U0 Renesas Electronics America, R5F21226JFP#U0 Datasheet - Page 365
![IC R8C/22 MCU FLASH 48LQFP](/photos/28/61/286102/48-lqfp__plqp0048kb-a_sml.jpg)
R5F21226JFP#U0
Manufacturer Part Number
R5F21226JFP#U0
Description
IC R8C/22 MCU FLASH 48LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/22r
Datasheet
1.R5F21237DFPU0.pdf
(551 pages)
Specifications of R5F21226JFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
For Use With
R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21226JFP#U0R5F21226JFP#U1
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
R5F21226JFP#U0R5F21226JFP#V0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 365 of 551
- Download datasheet (6Mb)
R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
16.3.3.5
In slave receive mode, the master device outputs the transmit clock and data, and the slave device returns an
acknowledge signal.
Figure 16.39 and Figure 16.40 show the Operation Timing in Slave Receive Mode (I
The receive procedure and operation in slave receive mode are shown below.
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set the WAIT and MLS bits in
(2) When the slave address matches at the 1st frame after detecting the start condition, the slave device
(3) Read the ICDRR register every time the RDRF bit is set to 1. If the 8th clock falls while the RDRF bit is
(4) Reading the last byte is performed by reading the ICDRR register as well.
the ICMR register and CKS0 to CKS3 bits in the ICCR1 register (initial setting). Set the TRS and MST
bits in the ICCR1 register to 0 and wait until the slave address matches in slave receive mode.
outputs the level set in the ACKBT bit in the ICIER register to the SDA pin at the rise of the 9th clock.
Since the RDRF bit in the ICSR register is set to 1 simultaneously, perform the dummy-read (the read
data is unnecessary because of showing slave address and R/W).
set to 1, the SCL signal is fixed “L” until the ICDRR register is read. The setting change of the
acknowledge signal which returns to master device before reading the ICDRR register reflects the
following transfer frame.
Slave Receive Operation
Page 343 of 501
16. Clock Synchronous Serial Interface
2
C Bus Interface Mode).
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