R5F21226JFP#U0 Renesas Electronics America, R5F21226JFP#U0 Datasheet - Page 547
![IC R8C/22 MCU FLASH 48LQFP](/photos/28/61/286102/48-lqfp__plqp0048kb-a_sml.jpg)
R5F21226JFP#U0
Manufacturer Part Number
R5F21226JFP#U0
Description
IC R8C/22 MCU FLASH 48LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/22r
Datasheet
1.R5F21237DFPU0.pdf
(551 pages)
Specifications of R5F21226JFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
For Use With
R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21226JFP#U0R5F21226JFP#U1
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
R5F21226JFP#U0R5F21226JFP#V0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Rev.
1.10
REVISION HISTORY
Oct 31, 2007
Date
Page
363
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367
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448
449
Figure 17.8; Bit name in the TRAMR register:
“MOD0 to 2 bits” → “Bits TMOD0 to TMOD2”
Figure 17.9; Procedure of Hardware LIN Clear the status flags:
“LINST register ← 0” → “LINST register ← 1”
Figure 17.11; Bit name in the LINST register:
“SCDCT flag” → “BCDCT flag”
Figure 17.12; Procedure of Hardware LIN Clear the status flags:
“LINST register ← 0” → “LINST register ← 1”
Figure 19.2; NOTE4 revised.
Table 19.2; Stop Condition revised.
Figure 19.4; NOTE4 revised.
Figure 19.6; NOTE4 revised.
Figure 19.10 revised. SW5 added.
19.6; the six line from the bottom:
“A/D conversion mode with” → “A/D conversion mode without”
19.7 revised.
Table 20.2; Function of CPU Rewrite Mode:
“any area other than the flash memory” → “the RAM”
Figure 20.4; NOTE1 revised.
Table 20.3; EW1 Mode:
“ROM area” → “ROM or RAM area”
20.4.1 and 20.4.2;
“td(SR-ES)” → “td(SR-SUS)”
20.4.2.4; the third line from the top:
“in other than the flash memory” → “transferred to the RAM”
20.4.2.15 revised.
Figure 20.5; NOTE3 and NOTE5 revised.
Figure 20.7; NOTE5 revised.
Figure 20.9;
“any area other than the flash memory” → “the RAM”
Figure 20.11;
• “any area other than the flash memory” → “the RAM”
• “15us” → “30us”
• NOTE4 deleted.
20.4.3.4 revised.
Figure 20.13 revised and NOTE4 added.
Figure 20.15 revised and NOTE4 added.
Table 20.7; MODE pin revised.
Table 21.1 and Table 21.2 NOTE1; D version added.
Table 21.3 NOTE1; D version added.
Table 21.4; NOTE1 revised.
R8C/22 Group, R8C/23 Group Hardware Manual
C - 24
Description
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