SAF-TC1130-L150EB BB Infineon Technologies, SAF-TC1130-L150EB BB Datasheet - Page 20

• Manufacturer Part Number: SAF-TC1130-L150EB BB
• Description: IC MCU 32BIT TRICOR 16KB LBGA208
• Manufacturer: Infineon Technologies
• Series: TC11xxr

Specifications of SAF-TC1130-L150EB BB

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Type: ROMless
• Ram Size: 144K x 8
• Voltage - Supply (vcc/vdd): 1.43 V ~ 1.58 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LSBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: FT1130L150EBBBNP; SAFTC1130L150EBBB; SP000099808

Table 2-1
Symbol
P4
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
HDRST
PORST
NMI
Data Sheet
Pin
R8
R9
N7
N6
P6
R7
R6
P5
N5
R5
T7
Pin Definitions and Functions (cont’d)
In
Out
I/O
I
O
I
I
I
O
I
O
O
I
O
O
O
I
I
O
I/O
I
I
PU/
PD
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUA
PUC Power-on Reset Input
PUC Non-Maskable Interrupt Input
1)
Functions
Port 4
Port 4 is an 8-bit bi-directional general purpose I/O
port which can be alternatively used for USB, MLI0 and
SCU.
USBCLK
TCLK0B
RCVI
TREADY0B
VPI
TVALID0B
VMI
TDATA0B
VPO
RCLK0B
VMO
RREADY0B
USBOE
RVALID0B
RDATA0B
BRKOUT_A
Hardware Reset Input/Reset Indication Output
Assertion of this bi-directional open-drain pin causes a
synchronous reset of the chip through external
circuitry. This pin must be driven for a minimum 4
clock cycles.
The internal reset circuitry drives this pin in response
to a power-on, hardware, watchdog and power-down
wake-up reset for a specific period of time. For a
software reset, activation of this pin is programmable.
A low level on PORST causes an asynchronous reset
of the entire chip. PORST is a fully asynchronous level
sensitive signal.
A high-to-low transition on this pin causes an
NMI-Trap request to the CPU.
14
differential signal
USB D- CMOS level mirror of
48 MHz input clock
USB data input
USB D+ CMOS level mirror of
differential signal
USB D+ CMOS level output
USB D- CMOS level output
Direction select for transmit or receive
MLI0 receive channel data input B
MLI0 transmit channel clock output B
MLI0 transmit channel ready input B
MLI0 transmit channel valid output B
MLI0 transmit channel data output B
MLI0 receive channel clock input B
MLI0 receive channel ready output B
MLI0 receive channel valid input B
OCDS Break Out A
General Device Information
V1.1, 2008-12
TC1130
f
CPU