SAF-TC1130-L150EB BB Infineon Technologies, SAF-TC1130-L150EB BB Datasheet - Page 38

• Manufacturer Part Number: SAF-TC1130-L150EB BB
• Description: IC MCU 32BIT TRICOR 16KB LBGA208
• Manufacturer: Infineon Technologies
• Series: TC11xxr

Specifications of SAF-TC1130-L150EB BB

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Type: ROMless
• Ram Size: 144K x 8
• Voltage - Supply (vcc/vdd): 1.43 V ~ 1.58 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LSBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: FT1130L150EBBBNP; SAFTC1130L150EBBB; SP000099808

The EBU is used primarily for any Local Memory Bus (LMB) master accessing external
memories. The EBU controls all transactions required for this operation and in particular
handles the arbitration between the internal EBU master and the external EBU master.
The types of external devices/bus modes controlled by the EBU are:
• Intel-style peripherals (separate RD and WR signals)
• ROMs, EPROMs
• Static RAMs
• PC100 and PC133 SDRAMs (Burst Read/Write Capacity/Multi-Bank/Page support)
• Specific types of Burst Mode Flash devices
• Special support for external emulator/debug hardware
Features:
• Supports 64-bit Local Memory Bus (LMB)
• Supports external bus frequency: internal LMB frequency = 1:1 or 1:2
• Provides highly programmable access parameters
• Supports Intel-style peripherals/devices
• Supports PC100 and PC133 (runs in maximum 120 MHz) SDRAM (burst access,
• Supports 16- and 32-bit SDRAM data bus and 64-,128-, and 256-Mbit devices
• Supports Burst Flash devices
• Supports Multiplexed access (address and data on the same bus) when PC100 and
• Supports data buffering: Code Prefetch Buffer, Read/Write Buffer
• External master arbitration compatible to C166 and other TriCore™ devices
• Provides 4 programmable address regions (1 dedicated for emulator)
• Provides a CSGLB signal, bit programmable to combine one or more CS lines for
• Provides RMW signal reflecting read-modify-write action
• Supports Little Endian byte ordering
• Provides signal for controlling data flow of slow-memory buffer
Data Sheet
multibanking, precharge, refresh)
PC133 SDRAM are not presented on the external bus
buffer control
32
Functional Description
V1.1, 2008-12
TC1130