SAK-C161JC-LF CA Infineon Technologies, SAK-C161JC-LF CA Datasheet - Page 38

• Manufacturer Part Number: SAK-C161JC-LF CA
• Description: IC MCU 16BIT 256KB TQFP-128-2
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAK-C161JC-LF CA

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SLDM, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 93
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 128-LFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: SAKC161JCLFCA; SP000057699

C161CS/JC/JI-32R
C161CS/JC/JI-L
Parallel Ports
The C161CS/JC/JI provides up to 93 I/O lines which are organized into eight input/output
ports and one input port. All port lines are bit-addressable, and all input/output lines are
individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O
ports are true bidirectional ports which are switched to high impedance state when
configured as inputs. The output drivers of five I/O ports can be configured (pin by pin)
for push/pull operation or open-drain operation via control registers, Port 9 provides
open-drain-only drivers. During the internal reset, all port pins are configured as inputs.
The input threshold of Port 2, Port 3, Port 4, Port 6, and Port 7 is selectable (TTL or
CMOS like), where the special CMOS like input threshold reduces noise sensitivity due
to the input hysteresis. The input threshold may be selected individually for each byte of
the respective ports.
All port lines have programmable alternate input or output functions associated with
them. All port lines that are not used for these alternate functions may be used as
general purpose IO lines.
PORT0 and PORT1 may be used as address and data lines when accessing external
memory, while Port 4 outputs the additional segment address bits A23/19/17 … A16 in
systems where segmentation is enabled to access more than 64 KBytes of memory.
Port 2, Port 7, and parts of PORT1 are associated with the capture inputs or compare
outputs of the CAPCOM units.
Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select
signals.
Port 3 includes alternate functions of timers, serial interfaces, the optional bus control
signal BHE, and the system clock output CLKOUT (or the programmable frequency
output FOUT).
Port 5 is used for the analog input channels to the A/D converter or timer control signals.
The edge characteristics (transition time) and driver characteristics (output current) of
the C161CS/JC/JI’s port drivers can be selected via the Port Output Control registers
(POCONx).
Data Sheet
34
V3.0, 2001-01