SAK-TC1796-256F150E BC Infineon Technologies, SAK-TC1796-256F150E BC Datasheet - Page 114
![no-image](/images/manufacturer_photos/0/3/327/infineon_technologies_sml.jpg)
SAK-TC1796-256F150E BC
Manufacturer Part Number
SAK-TC1796-256F150E BC
Description
IC MCU 32BIT FLASH BGA-416
Manufacturer
Infineon Technologies
Series
TC17xxr
Datasheet
1.SAK-TC1796-256F150E_BE.pdf
(134 pages)
Specifications of SAK-TC1796-256F150E BC
Core Processor
TriCore
Core Size
32-Bit
Speed
150MHz
Connectivity
ASC, CAN, EBI/EMI, MLI, MSC, SSC
Peripherals
DMA, POR, WDT
Number Of I /o
123
Program Memory Size
2MB (2M x 8)
Program Memory Type
FLASH
Ram Size
256K x 8
Voltage - Supply (vcc/vdd)
1.42 V ~ 1.58 V
Data Converters
A/D 44x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
416-BGA
Data Bus Width
32 bit
Data Ram Size
256 KB
Interface Type
2xASC, 2xSSC, 2xMSC, 2xMLI
Maximum Clock Frequency
150 MHz
Number Of Programmable I/os
123
Number Of Timers
260
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 10 bit, 12 bit, 44 Channel
Packages
P-BGA-416
Max Clock Frequency
150.0 MHz
Sram (incl. Cache)
256.0 KByte
Can Nodes
4
A / D Input Lines (incl. Fadc)
44
Program Memory
2.0 MB
For Use With
B158-H8537-G2-X-7600IN - KIT STARTER TC179X FAMILY
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Other names
SAKTC1796256F150EBCT
SP000097527
SP000097528
SP000097527
SP000097528
Figure 33
Note: The specified PLL jitter values are valid if the capacitive load at the External Bus
Note: The maximum peak-to-peak noise on the Core Supply Voltage (measured
Data Sheet
Unit (EBU) is limited to
between
a peak-to-peak voltage of
appropriate blocking of the Core Supply Voltage as near as possible to the supply
pins and using PCB supply and ground planes.=20pF.
D
P
±4.0
±3.5
±3.0
±2.5
±2.0
±1.5
±1.0
±0.5
±0.0
ns
0
D
P
K
Approximated Maximum Accumulated PLL Jitter for Typical CPU
Clock Frequencies
P
V
= Max. jitter
= Number of consecutive f
= K-divider of PLL
DD
2
at pin E23 and
f
CPU
4
= 50 MHz (K = 8)
C
L
=20pF.
6
V
f
V
CPU
SS
PP
CPU
at pin D23, or adjacent supply pairs) is limited to
8
= 30mV. This condition can be achieved by
(detail)
periods
114
10
f
CPU
f
CPU
= 50 MHz (K = 14)
12
= 100 MHz (K = 7)
14
f
f
CPU
CPU
Electrical Parameters
= 150 MHz (K = 4)
= 100 MHz (K = 4)
TC1976_PLL_DETAIL
16
18
V1.0, 2008-04
TC1796
20
P