SAK-TC1796-256F150E BC Infineon Technologies, SAK-TC1796-256F150E BC Datasheet - Page 27
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SAK-TC1796-256F150E BC
Manufacturer Part Number
SAK-TC1796-256F150E BC
Description
IC MCU 32BIT FLASH BGA-416
Manufacturer
Infineon Technologies
Series
TC17xxr
Datasheet
1.SAK-TC1796-256F150E_BE.pdf
(134 pages)
Specifications of SAK-TC1796-256F150E BC
Core Processor
TriCore
Core Size
32-Bit
Speed
150MHz
Connectivity
ASC, CAN, EBI/EMI, MLI, MSC, SSC
Peripherals
DMA, POR, WDT
Number Of I /o
123
Program Memory Size
2MB (2M x 8)
Program Memory Type
FLASH
Ram Size
256K x 8
Voltage - Supply (vcc/vdd)
1.42 V ~ 1.58 V
Data Converters
A/D 44x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
416-BGA
Data Bus Width
32 bit
Data Ram Size
256 KB
Interface Type
2xASC, 2xSSC, 2xMSC, 2xMLI
Maximum Clock Frequency
150 MHz
Number Of Programmable I/os
123
Number Of Timers
260
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 10 bit, 12 bit, 44 Channel
Packages
P-BGA-416
Max Clock Frequency
150.0 MHz
Sram (incl. Cache)
256.0 KByte
Can Nodes
4
A / D Input Lines (incl. Fadc)
44
Program Memory
2.0 MB
For Use With
B158-H8537-G2-X-7600IN - KIT STARTER TC179X FAMILY
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Other names
SAKTC1796256F150EBCT
SP000097527
SP000097528
SP000097527
SP000097528
Table 2
Symbol
P10
P10.0
P10.1
P10.2
P10.3
Dedicated Peripheral I/Os
SLSO0
SLSO1
MTSR0
MRST0
SCLK0
SLSI0
Data Sheet
Pins
A21
B21
C21
D21
AE14
AC15 O
AF15
AE15
AF14
AD15 I
Pin Definitions and Functions (cont’d)
I/O Pad
I
I
I
I
I
O
O
I
I
O
I/O
Class
A1
A2
Power
Supply
V
V
DDP
DDP
27
Functions
Hardware Configuration Inputs / Port 10
These inputs are boot mode (hardware
configuration) control inputs. They are
latched with the rising edge of HDRST.
Port 10 input line 0 / HWCFG0
Port 10 input line 1 / HWCFG1
Port 10 input line 2 / HWCFG2
Port 10 input line 3 / HWCFG3
After reset (HDRST = 1) the state of the
Port 10 input pins may be modified from the
reset configuration state. There actual state
can be read via software (P10_IN register).
During normal operation input HWCFG1
serves as emergency shut-off control input
for certain I/O lines (e.g. GPTA related
outputs).
SSC0 Slave Select Output Line 0
SSC0 Slave Select Output Line 1
SSC0 Master Transmit Output /
SSC0 Slave Receive Input
SSC0 Master Receive Input /
SSC0 Slave Transmit Output
SSC0 Clock Input/Output
SSC0 Slave Select Input
General Device Information
V1.0, 2008-04
TC1796