SAK-TC1796-256F150E BC Infineon Technologies, SAK-TC1796-256F150E BC Datasheet - Page 38
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SAK-TC1796-256F150E BC
Manufacturer Part Number
SAK-TC1796-256F150E BC
Description
IC MCU 32BIT FLASH BGA-416
Manufacturer
Infineon Technologies
Series
TC17xxr
Datasheet
1.SAK-TC1796-256F150E_BE.pdf
(134 pages)
Specifications of SAK-TC1796-256F150E BC
Core Processor
TriCore
Core Size
32-Bit
Speed
150MHz
Connectivity
ASC, CAN, EBI/EMI, MLI, MSC, SSC
Peripherals
DMA, POR, WDT
Number Of I /o
123
Program Memory Size
2MB (2M x 8)
Program Memory Type
FLASH
Ram Size
256K x 8
Voltage - Supply (vcc/vdd)
1.42 V ~ 1.58 V
Data Converters
A/D 44x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
416-BGA
Data Bus Width
32 bit
Data Ram Size
256 KB
Interface Type
2xASC, 2xSSC, 2xMSC, 2xMLI
Maximum Clock Frequency
150 MHz
Number Of Programmable I/os
123
Number Of Timers
260
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 10 bit, 12 bit, 44 Channel
Packages
P-BGA-416
Max Clock Frequency
150.0 MHz
Sram (incl. Cache)
256.0 KByte
Can Nodes
4
A / D Input Lines (incl. Fadc)
44
Program Memory
2.0 MB
For Use With
B158-H8537-G2-X-7600IN - KIT STARTER TC179X FAMILY
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Other names
SAKTC1796256F150EBCT
SP000097527
SP000097528
SP000097527
SP000097528
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Features of the Data Flash
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Data Sheet
JEDEC standard based command sequences for PFLASH control
– Write state machine controls programming and erase operations
– Status and error reporting by status flags and interrupt
Margin check for detection of problematic PFLASH bits
128 Kbyte on-chip data Flash memory, organized in two 64 Kbyte banks
Usable for data storage with EEPROM functionality
128 Byte program interface
– 128 bytes are programmed into one DFLASH page by one step/command
64-bit read interface (no burst transfers)
Dynamic correction of single-bit errors during read access
Detection of double bit errors
Fixed sector architecture
– Two 64 Kbyte banks/sectors
– Each sector separately erasable
Configurable read protection (combined with write protection) for complete DFLASH
together with PFLASH read protection
Password mechanism to temporarily disable write and read protection
Erasing/programming of one bank possible while reading data from the other bank
Programming of one bank possible while erasing the other bank
On-chip generation of programming voltage
DFLASH is delivered in erased state (read all zeros)
JEDEC-standard based command sequences for DFLASH control
– Write state machine controls programming and erase operations
– Status and error reporting by status flags and interrupt
Margin check for detection of problematic DFLASH bits
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Functional Description
V1.0, 2008-04
TC1796