MCIMX31LCVMN4C Freescale Semiconductor, MCIMX31LCVMN4C Datasheet - Page 32

IC MPU MAP I.MX31L 473-MAPBGA

MCIMX31LCVMN4C

Manufacturer Part Number
MCIMX31LCVMN4C
Description
IC MPU MAP I.MX31L 473-MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX31r
Datasheets

Specifications of MCIMX31LCVMN4C

Core Processor
ARM11
Core Size
32-Bit
Speed
400MHz
Connectivity
1-Wire, ATA, EBI/EMI, FIR, I²C, MMC/SD, PCMCIA, SIM, SPI, SSI, UART/USART, USB, USB OTG
Peripherals
DMA, LCD, POR, PWM, WDT
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.22 V ~ 3.3 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
473-MAPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Program Memory Size
-
Data Converters
-

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Quantity
Price
Part Number:
MCIMX31LCVMN4C
Manufacturer:
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Quantity:
10 000
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Manufacturer:
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1
2
Electrical Characteristics
4.3.9
This section provides electrical parametrics and timings for EMI module.
4.3.9.1
The NFC supports normal timing mode, using two flash clock cycles for one access of RE and WE. AC
timings are provided as multiplications of the clock cycle and fixed delay.
and
for normal mode, and
32
Phase lock time
Maximum allowed PLL supply voltage ripple
Maximum allowed PLL supply voltage ripple
Maximum allowed PLL supply voltage ripple
PLL output clock phase jitter
PLL output clock period jitter
The user or board designer must take into account that the use of a frequency other than 26 MHz would require adjustment to
the DPTC–DVFS table, which is incorporated into operating system code.
The PLL reference frequency must be ≤ 35 MHz. Therefore, for frequencies between 35 MHz and 70 MHz, program the
predivider to divide by 2 or more. If the CKIH frequency is above 70 MHz, program the predivider to 3 or more. For PD bit
description, see the reference manual.
Figure 25
EMI Electrical Specifications
NAND Flash Controller Interface (NFC)
depict the relative timing requirements among different signals of the NFC at module level,
NFCLE
NFCE
NFWE
NFALE
NFIO[7:0]
Parameter
Table 29
Figure 22. Command Latch Cycle Timing DIagram
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
lists the timing parameters.
Table 28. DPLL Specifications (continued)
NF6
NF3
NF1
Min
Command
NF8
NF5
Typ
NF9
NF7
Max
100
420
5.2
NF2
25
20
25
NF4
Unit
mV F
mV 50 kHz < F
mV F
ns
ps
µs
Figure
In addition to the frequency
Measured on CLKO pin
Measured on CLKO pin
modulation
modulation
22,
< 50 kHz
> 300 kHz
Figure
modulation
Freescale Semiconductor
Comments
23,
< 300 kHz
Figure
24,

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