SC68C652BIB48,157 NXP Semiconductors, SC68C652BIB48,157 Datasheet - Page 10

• Manufacturer Part Number: SC68C652BIB48,157
• Description: IC UART DUAL 48LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC68C652BIB48,157

• Features: 2 Channels
• Number Of Channels: 2, DUART
• Fifo's: 32 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-LFQFP
• Voltage: 2.25 V ~ 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935278766157; SC68C652BIB48; SC68C652BIB48

NXP Semiconductors
SC68C652B_2
Product data sheet
6.4 Hardware flow control
6.5 Software flow control
Table 5.
When automatic hardware flow control is enabled, the SC68C652B monitors the CTSn pin
for a remote buffer overflow indication and controls the RTSn pin for local buffer overflows.
Automatic hardware flow control is selected by setting EFR[6] (RTS) and EFR[7] (CTS) to
a logic 1. If CTSn transitions from a logic 0 to a logic 1 indicating a flow control request,
ISR[5] will be set to a logic 1 (if enabled via IER[6:7]), and the SC68C652B will suspend
TXn transmissions as soon as the stop bit of the character in process is shifted out.
Transmission is resumed after the CTSn input returns to a logic 0, indicating more data
may be sent.
With the auto-RTS function enabled, an interrupt is generated when the receive FIFO
reaches the programmed trigger level. The RTSn pin will not be forced to a logic 1 (RTS
off), until the receive FIFO reaches the next trigger level. However, the RTSn pin will return
to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level below the
programmed trigger level. However, under the above described conditions, the
SC68C652B will continue to accept data until the receive FIFO is full.
When software flow control is enabled, the SC68C652B compares one or two sequential
receive data characters with the programmed Xon or Xoff character value(s). If received
character(s) match the programmed Xoff values, the SC68C652B will halt transmission
as soon as the current character(s) has completed transmission. When a match occurs,
the receive ready (if enabled via Xoff IER[5]) flags will be set and the interrupt output pin
(if receive interrupt is enabled) will be activated. Following a suspension due to a match of
the Xoff characters’ values, the SC68C652B will monitor the receive data stream for a
match to the Xon1/Xon2 character value(s). If a match is found, the SC68C652B will
resume operation and clear the flags (ISR[4]).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0.
Following reset, the user can write any Xon/Xoff value desired for software flow control.
Different conditions can be set to detect Xon/Xoff characters and suspend/resume
transmissions. When double 8-bit Xon/Xoff characters are selected, the SC68C652B
compares two consecutive receive characters with two software flow control 8-bit values
(Xon1, Xon2, Xoff1, Xoff2) and controls TXn transmissions accordingly. Under the above
described flow control mechanisms, flow control characters are not placed (stacked) in the
user accessible receive data buffer or FIFO. When using a software flow control, the
Xon/Xoff characters cannot be used for data transfer.
In the event that the receive buffer is overfilling and flow control needs to be executed, the
SC68C652B automatically sends an Xoff message (when enabled) via the serial TXn
output to the remote modem. The SC68C652B sends the Xoff1/Xoff2 characters as soon
Selected trigger level
(characters)
8
16
24
28
Flow control mechanism
Rev. 02 — 2 November 2009
IRQ pin activation
RX
8
16
24
28
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
TX
16
8
24
30
Negate RTS or
send Xoff
8
16
24
28
SC68C652B
© NXP B.V. 2009. All rights reserved.
Assert RTS or
send Xon
0
7
15
23
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